Embedded Solutions
Page 45 of 71
IP Control1 Register (IPx CR1)
IP0/IP1/IP2/IP3/IP4 - Offset 0x084/0x0E4/0x144/0x1A4/0x204
Bit(s)
Description
Attribute Default
31:29
IPx Data-in Timing Mux
000 = Normal Timing mode:
Warning: Non Zero Values not intended for normal use.
Errors will occur with non-zero values.
Multiplexors were added the PCIeIP Data and ACK* paths to
enable the IP interface’s to meet/exceed the 0ns setup timing.
R/W
0h
28:7
Reserved
RO
0h
6:5
Increment Read Disable
-
Word Address Offset
Selects which 16-bit word is accessed on a 32bit or 64bit read
relative to the accesses address. Only has an effect when the
Address Increment Read Disable bit is asserted.
For 64 bit accesses
11 = Word3 is accessed four times.
10 = Word2 is accessed four times.
01 = Word1 is accessed four times.
00 = Word0 is accessed four times.
For 32 bit accesses
X1 = Word1 is accessed twice.
X0 = Word0 is accessed twice.
32 bit data accesses are required to be 32bit address aligned.
64 bit data accesses are required to be 64bit address aligned.
R/W
0h
4
Address Increment Read Disable
– For a 32 bit or 64bit PCI
Express read access each IP Read access uses the same
Word aligned address. The Word address used is specified
with the Increment Read Disable – Word Address Offset bits
(bits 6:5 above).
See Write version in IPx CR0
R/W
0h
3:0
User Control/Status bits
– Read/Writable bits for user use.
R/W
0h
