Embedded Solutions
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IPx Bus Error event – When PCIeIP initiates a R/W access to an IPx, it waits for the IP
to respond with ACK*, if ACK* is not asserted within a predefined number of IP clocks
this is a Bus Error and the logic sets IPx ISR bit [2] = 1. The number of clocks is
determined by the frequency of operation and the setting of the Bus Error timeout select
bit (IPx Control0 Register bit [12]). The default/program values are 127/255 IP clocks at
32MHz and 63/127 IP clocks at 8MHz.
IPx Bus Error function and purpose – Upon the occurrence of a Bus Error PCIeIP will
either drop the write or complete the read using all F’s for the data, then return the IPx
state machines to their idle state so that they are able to process the next transaction.
Bus Error interrupts are used during initialization to scan the IPx ports to detect if an IP
is present on the IPx port. Once a system is initialized and running a Bus Error interrupt
would normally be considered a serious system error.
IPx Interrupt Requests (IntReq[1:0]*) – IPx Interrupt Requests source bits (IPx ISR bits
[1:0]) are read only status bits that reflect the IPx’s IntReq[1:0]* pin states after being
synchronized, inverted and filtered for 2 clocks. Behavior Note: Since the IPx Interrupt
Request source bits (IPx ISR bit [1:0]) essentially reflect the IntReq[1:0]* pins it is
possible they can set their respective ISR bit, but the IPx ISR bit [1:0] source could be
de-asserted/cleared when read if the IP toggles the IntReq[1:0]* pin(s).
This would be
considered unusual behavior. Dynamic Engineering IP Modules do not operate in this
manner.
PCIeIP MSI Interrupts
Per the PCI Express specification, when a PCI Express device supports both virtualized
INTx messages and MSI, only one of the mechanism will be enabled at any given time.
When PCIeIP comes out of reset it is in INTA# mode as both the Interrupt Disable and
MSI Enable bits are 0 by default. Also per spec, setting the MSI Enable bit in the
Message Control Register (offset 0x72) disables the PCIeIP ability to use INTx
messages and enables MSI.
Before enabling MSI the Host needs to write valid values in the Message Address and
Message Data registers. It should also leave the Multiple Message Enable field at the
default value of 0x0h as PCIeIP only requests and indicates support for one MSI via the
Multiple Message Capable bits = 0x0h. See section 2.0 for a complete summary of MSI
registers/bits.
