Embedded Solutions
Page 38 of 71
PCIeIP register map (continued) – Offset 0x000 to 0x1FC
96 bytes for each set of IP Registers
Offset
Register
Description
0x1A0
IP3 Control0
IP3 Channel behavior & data flow control
0x1A4
IP3 Control1
IP3 Channel behavior & data flow control
0x1A8
IP3 Interrupt Status
IP3 Interrupts
0x1AC
IP3 Interrupt Control
IP3 Interrupt Masks
0x1B0
Reserved
Reserved for IP3
0x1B4
IP3 Transfer Monitor
IP3 ACK*/Channel Transfer & Activity Monitor
0x1B8-1FF
Reserved
Reserved for IP3
Offset
Register
Description
0x200
IP4 Control0
IP4 Channel behavior & data flow control
0x204
IP4 Control1
IP4 Channel behavior & data flow control
0x208
IP4 Interrupt Status
IP4 Interrupts
0x20C
IP4 Interrupt Control
IP4 Interrupt Masks
0x210
Reserved
Reserved for IP4
0x214
IP4 Transfer Monitor
IP4 ACK*/Channel Transfer & Activity Monitor
0x218-25F
Reserved
Reserved for IP4
416 reserved bytes
Offset
Register
Description
0x260-3FF
Reserved
Reserved
Figure 6
PCIeIP Register Address Map
Register summary notes: Global and IP register locations are the same for the VPX2IP,
PCIe3IP and PCIe5IP. Registers for IP’s that are not implemented are reserved. Writes
to reserved registers are dropped and reads return 0x0000_0000’s. For the VPX2IP
register locations between 0x140 to 0x25F are reserved. For the PCIe3IP register
locations between 0x1A0 to 0x25F are reserved.
