Embedded Solutions
Page 22 of 71
PCIeIP Resets, Clocks, & Bus Error
PCI Express Reset (PERST#) summary
There are two types of resets in PCIe, both of which are supported by the PCIeIP, they
are:
Fundamental Reset (cold or warm) – assertion of PERST#
o
Cold - Power applied to a cold (non-powered) system.
o
Warm – Power is up/good before & during assertion of PERST#.
Hot Reset – TS1 Ordered-Sets sent with bit [0] of symbol 5 asserted for 2ms.
Per the PCIe specification:
The minimum PERST# assertion time is 100ms from the time power is stable.
o
In order to be configured and ready for enumeration before PERST# is de-
asserted PCIeIP downloads the FPGA configuration file from a parallel
Flash.
PERST# signal is asserted and de-asserted asynchronously.
IP Reset* Summary
Reset* (IPx_RESETN) signal rules from Vita Spec:
When asserted, Reset* must be asserted for a minimum of 200ms, there is no
maximum.
Can be asserted asynchronously, and must be de-asserted synchronously.
+5V must be monitored and reset asserted if power falls below minimum spec
Reset* is the logical OR of Power monitoring reset and the system reset.
IP module documents must clearly state the time needed from Reset* de-
assertion until the IP module is initialized.
When Reset* is asserted IP’s must terminate any cycle, interrupts, DMA requests
or future requests.
The PCIeIP supports all Carrier card rules for Reset*.
