Embedded Solutions
Page 14 of 71
The PCIeIP Architecture is the foundation for all the devices in the PCIeIP Carrier
Series. The PCIe3IP Block Diagram (Figure 1) and PCIe3IP FPGA Block Diagram
(Figure 2) illustrate a 3IP channel design using the PCIeIP Architecture. To create the
PCIe5IP two additional IP channels (IP3 & IP4 – not shown) are implemented. To create
the VPX2IP the IP2 channel is removed.
PCIe3IP Block Diagram
Power Circuits
Monitors & Power in range LEDs
P12V
CPLD Parallel
FPGA Loader
PERp/n0
16 bit – 90ns
FLASH
JTAG
Header
32MHz
OSC
PETp/n0
Lattice ECP3 FPGA
CFG & TEST
P5VGOOD
Parallel CFG & Data
USER DIP Switch Inputs
TDO
PCIe /-
M12V
P5V
3.3V
1.2V
CFG & TEST
DIP Switch
USER
DIP Switch
USER LED [7:0]
x1
PCI
Express
Edge
Fingers
Connector
TDI
TDI
TDO
Lattice ECP3 FPGA
PCI
Express
Core
PERST#
IP0
Interface
IP0
IP0 ACK* Activity LED
``
Carrier
IP0 Logic
Connector
SMT
3.3V – 5V
Level
Shifter
``
HDR_50
IP0
RT Angle
Header
With
Ejectors
IP0
Carrier
IO
Connector
SMT
IP1
Interface
IP1
IP1 ACK* Activity LED
``
Carrier
IP1 Logic
Connector
SMT
3.3V – 5V
Level
Shifter
``
HDR_50
IP1
Vertical
Header
IP1
Carrier
IO
Connector
SMT
IP2
Interface
IP2
IP2 ACK* Activity LED
``
Carrier
IP2 Logic
Connector
SMT
3.3V – 5V
Level
Shifter
``
HDR_50
IP2
Vertical
Header
IP2
Carrier
IO
Connector
SMT
Figure 1
PCIe3IP Block Diagram
