Embedded Solutions
Page 11 of 71
VPX2IP/PCIe3IP/PCIe5IP has a total of 15/16/18 LED’s to indicate various status. 2/3/5
LED’s are used and light to indicate ACK* activity on each of the 2/3/5 IP channels. 5
LED’s are used with 5 independent voltage monitoring circuits to accurately detect if any
of the board’s voltages are out of range. One LED for each power monitoring circuit,
when the LED is on the voltage is in range, if the LED is off the voltage is out of range.
Eight (8) user controllable LED's are supplied. Each LED is programmable with one of
sixteen possible sources to provide a variety of status. The 4bit LED select field in the
Switch and LED control register is used to determine each LED’s meaning. One of the
selections allows the user to directly control the LED’s. The default selection uses 4
LED’s to reflect PCIe link status, when all four of the lower four LED’s are on they
indicate a working link.
Two 8 bit "dip switches" are provided on the PCIeIP. One 8 bit dip switch is for user
configuration and is readable via the Switch and LED control register. The other 8 bit dip
switch is for board configuration and test purposes (see Board Features section for
details).
Power-on PCIe PERST# reset is used to reset the entire PCIeIP. Each IP Reset* is
asserted as long as PERST# is asserted. Once PERST# is de-asserted each IP’s clock
starts toggling, and each IP Reset* will remain asserted until a 256ms timer expires.
Once the timer expires IP Reset* de-asserts synchronously with that IP’s CLK. Two
separate control register reset bits are provided for each IP. One only asserts IP Reset*,
and one asserts IP Reset* and resets that PCIeIP’s IP channel/FIFO.
To meet the PCI Express specification requirement for PCIe core initialization within
100mS from PERST# de-assertion; PCIeIP implements a 16 bit wide 90ns Flash in
conjunction with a CPLD to configure the FPGA via its parallel configuration port. With
this architecture, PCIeIP beats this aggressive specification by a comfortable margin.
For the PCIe3IP/PCIe5IP the IO’s for each IP are brought out to their own 50 pin
headers. For the VPX2IP, stuffing options route the IO to either the Condo header or the
VPX rear connector. All IO signals for each PCIeIP board are routed carefully with
matched length and impedance control. Differential routing techniques are used to
support operation with LVDS, RS485 and other differential electrical standards as well
as single ended systems – analog, TTL IO etc. Please see the pin-out tables later in
this manual for the mapping of IP IO to header.
For the PCIe3IP/PCIe5IP the 50 pin header in the first position is mounted [right angle
header] to be accessible through the bezel. The second, third, (PCIe3IP) fourth and
fifth positions (PCIe5IP) have traditional vertical headers.
