Embedded Solutions
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A Bus Error event occurs when the PCIeIP initiates an R/W access to an IP and the IP
doesn’t assert its ACK* within the predefined number of IP clocks. The number of clocks
the PCIeIP waits is determined by the frequency of operation and the setting of the Bus
Error timeout select bit. Upon the occurrence of a Bus Error that IP channel sets its Bus
Error Interrupt bit (IPx ISR bit [2] = 1) and an interrupt can be generated.
In normal operation the PCIeIP receives PCI Express packets to write or read up to
64bits on the IP bus. Byte enables are also received in the packet which the PCIeIP
uses to determine if a byte, word, Dword, two Dword, or four Dword R/W transaction will
be generated on the IP bus. If ACK* is not received for a write, the write transaction is
terminated, data is discarded and credits are updated accordingly.
If ACK* is not received for a read, then depending upon the transfer size and/or byte
enables a read will return different completion data. For a 64bit transfer, the PCIeIP
generates two separate 32bit accesses, as such the data returned when ACK* isn’t
provided is the same as when an ACK* isn’t provided during two 32bit transfers back to
back. A 32bit transfer causes the PICeIP to do two 16bit IP transfers, if ACK* isn’t
received for the first 16bit IP transaction 0xFFFF_FFFF will be provided and the second
16bit IP transaction will not be generated on the IP bus. If the ACK* is received for the
first IP transaction, but not the second, the read will have 0xFFFF in the upper word and
valid data in the lower word of the 32 bit PCIe read completion data field.
For non 32bit reads where an ACK* does not occur 0xFFFF will be returned for a Dword
access that has a valid byte enable(s). A word in the 32bit completion data field where
the byte enables are not asserted will have 0x0000 in them regardless if there is a Bus
Error or not. Therefore, the completion data returned depends upon the each IP
transfer’s byte enables and which transfer the IP doesn’t provide an ACK*.
When a Bus Error occurs the IP state machines will return to their idle state so that they
are able to process the next transaction. For all possible read combinations with bus
errors credits are updated accordingly.
Bus Error interrupts can, and are used during initialization to scan the IPx ports to detect
the presence of an IPx installed in a slot. Typically a driver will do a 32bit (or 16bit)
access of the slot’s/IP’s ID space, and if it detects either 0xFFFF_FFFF (or 0xFFFF) it
knows an IP is not installed in that slot. Once a system is initialized and running a Bus
Error interrupt is normally considered a serious system error.
