Embedded Solutions
Page 5 of 71
PRODUCT DESCRIPTION
9
THEORY OF OPERATION
16
PROGRAMMING
18
VPX2IP ADDRESS MAP
18
PCIE3IP ADDRESS MAP
19
PCIE5IP ADDRESS MAP
20
PCIEIP RESETS, CLOCKS, & BUS ERROR
22
IP CHANNEL TRANSFER ACTIVITY MONITOR AND LOGIC
26
PCIEIP INTERRUPTS
28
PCIEIP REGISTERS
37
LED DECODE TABLE
49
PCIEIP BOARD FEATURES
52
PCIeIP Carrier IP Logic Connector Pin Assignment
52
PCIeIP IP Carrier IO Connector to 50 Pin Header Assignment
53
VPX2IP IP Carrier Condo Header Connector Assignment – Option 1
53
VPX2IP IP Carrier Rear IO Connector Assignment – Option 2
54
PCIE3IP BOARD FEATURES
55
PCIe3IP DIP Switches
55
Table of Contents
