Embedded Solutions
Page 49 of 71
LED Decode Table
LED Select
= 0000 - Link and board status
LED
Signal Name
Description
LED[7:4] -
Reserved – 0x0 - LED’s are off
LED[3]
dl_up
Data Link Layer is up
LED[2]
l0
L0 – L0 state has been reached
LED[1]
poll
Polling – PCIe core is in the polling state
LED[0]
pll_lk
PLL Lock – PCIe SERDES clock is locked to PCIe ref clock
LED Select
= 0001 -
USER LED Control [7:0]
register bits
LED
Signal Name
Description
LED[7:0] USER LED’s[7:0]
USER LED Control [7:0]
register bits control LED[7:0]
LED Select
= 0010 –
Dip Switch Setting
LED[7:0] dip_switch[7:0]
LED is on when switch pin is logic high ‘1’
LED Select
= 0011 –
FPGA and Flash Switch Setting
LED
Signal Name
Description
LED[7:6]
-
Always off
LED[5:4]
flash_sel[1:0]
LED is on when switch pin is logic high ‘1’
LED[3]
-
Always off
LED[2:0]
fpga_sel[2:0]
LED is on when switch pin is logic high ‘1’
LED Select
= 0100 - IP0 Status
LED Select
= 0101 - IP1 Status
LED Select
= 0110 - IP2 Status
LED
Signal Name
Description
LED[7]
IPx Force Interrupt Force Interrupt asserted – ISR (offset 0x008) bit[3]
LED[6]
IPx Bus Error
Bus Error Interrupt asserted – ISR (offset 0x008) bit[2]
LED[5]
IPx Intreq1*
IRQN[1] asserted – ISR (offset 0x008) bit[1]
LED[4]
IPx Intreq0*
IRQN[0] asserted – ISR (offset 0x008) bit[0]
LED[3]
IPx_MemSpace
Memory access is in process or was the last IP access
LED[2]
IPx_IntSpace
INT access is in process or was the last IP access
LED[1]
IPx_IOSpace
IO access is in process or was the last IP access
LED[0]
IPx_IDSpace
ID access is in process or was the last IP access
