Embedded Solutions
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Once enabled, the key difference between PCIeIP’s MSI and INTA# interrupt generation
is that only one MSI packet will be sent to the Host to indicate an Interrupt assertion. No
MSI packet is generated or sent when the ISR interrupt bit or bits are cleared using a
W1C. The timing of when an MSI packet is sent in response to an assertion is identical
to when an INTA# assert packet is sent as described in previous sections.
When the PCIeIP generates and sends the MSI packet it uses the Message Address
and Data register values provided by the Host to create the MSI (Memory Write) packet.
PCIeIP Important Interrupt Notes
For predictable behavior users should only change the Level/Edge mode, Aggregation
enable, Aggregation and Interrupt de-assert timers when the system is in a quiescent
state or if all ISR Interrupts have been processed and all Interrupts are disabled
(Masked) by clearing all the IPx’s ICR Interrupt Enable [3:0] bits. Not doing so can lead
to Interrupts being lost when switching from Level to Edge mode in addition to other
unpredictable behavior.
When in INTA# mode any W1C to any bit in the ISR whether it is set or not will cause
PCIeIP to generate and send an INTA# Message packet that contains a Deassert_INTA
message code.
When the MSI Enable bit is set the INTA# functionality is disabled regardless of the
state of the Interrupt Disable bit, additionally the Interrupt Status bit is no longer relevant
and remains 0.
Assertion/de-assertion of the IPx ICR Interrupt enable bits [3:0] (i.e. Mask bits) when
their respective source bits in the IPx ISR are asserted can be used to mimic
assertion/de-assertion of the source interrupt as seen by the ISR.
