Embedded Solutions
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IP Interrupt Status Register (IPx ISR)
IP0/IP1/IP2/IP3/IP4 - Offset 0x088/0x0E8/0x148/0x1A8/0x208
These bits contain the Interrupt value/setting before the Mask is applied. See PCIeIP
Interrupts section for additional details regarding these interrupts.
Bit(s)
Description
Attribute Default
31:6
Reserved for additional IPx Interrupts and/or control
RO
0h
5
IPx Bus Error Interrupt Read
0 = Indicates a Bus Error has not occurred on a read.
1 = Indicates a Bus Error occurred on a read.
RW1C
0h
4
IPx Bus Error Interrupt Write
0 = Indicates a Bus Error has not occurred on a write.
1 = Indicates a Bus Error occurred on a write.
RW1C
0h
3
IPx Force/P5VGOODn Interrupt
0 = Interrupt not asserted, 1 = Interrupt asserted.
Interrupt that may be set from the following two sources:
1) User programmable interrupt set via this bit “IPx
Force” (IPx ISR bit [3]) which provides the user a
way to assert/de-assert an interrupt in a controlled
fashion for development or design purposes.
2) Is set due to detection of the 5 volt power source
being out of range.
R/W
0h
2
IPx Bus Error Interrupt
0
= No Bus Error has occurred.
1 = Bus Error occurred since reset or last W1C.
May also be cleared by W1C of ISR (0x008) bit [2] (IP0), bit
[6] (IP1), bit [10] (IP2) when in Level mode IPx ICR
(0x08C/0x0BC/0x0EC) bit [10] =1. This prevents more than
one Interrupt being generated per Bus Error in Level Mode.
Note: A Hardware Bus Error is an event which is captured and
held in this register and forwarded on to ISR if not masked.
RW1C
0h
1
IPx IntReq1* signal status/value.
0 = pin value is high/1/not asserted. 1= pin value is
low/0/asserted.
RO
-
0
IPx IntReq0* signal status/value.
0 = pin value is high/1/not asserted. 1= pin value is
low/0/asserted.
RO
-
