Embedded Solutions
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For example if 100 reads are in one IP’s receive FIFO and a new read is received for a
different IP, it will be routed into that IP’s receive FIFO.
The header credits are set to the maximum allowed by the PCIe core, which is 127, so
up to 127 combined IP read and write requests may be pending at any one time inside
the PCIeIP.
Once a register or IP access has completed processing a write or read, the appropriate
credit updates will be accumulated and sent to the core which will create Flow Control
DLL packet(s) to inform/update the Host that more space/credit is available inside the
PCIeIP. For the VPX2IP/PCIe3IP/PCIe5IP there are three/four/six possible read targets
and/or sources for read completion packets, they are: IP[1:0]/IP[2:0]/IP[4:0], and a
register access. When the read target has assembled the read completion packet it
stores it in its transmit FIFO as it must arbitrate for and then write the completion into
the transmit packet port of the PCIe core. The transmit packet arbiter is a round robin
arbiter. The transmit packet port won’t grant access until the core informs it is ready to
receive a packet.
