Embedded Solutions
Page 48 of 71
IPx Channel Transfer Monitor Register (IPx CTM)
IP0/IP1/IP2/IP3/IP4 - Offset 0x094/0x0F4/0x154/0x1B4/0x214
This register provides control of and access to IPx’s channel ACK* counter, additionally
it provides channel activity status. See IP Channel Transfer Activity Monitor and Logic
section for further application/usage details.
Bit(s)
Description
Attribute Default
31:29
Reserved
RO
0h
28
IPx Channel Busy
0 = No transfers pending in IPx FIFO or channel.
1 = Indicates at least one transfer is still pending in the
channel’s FIFO or the IP interface is still processing an
IP read or write cycle.
RO
0h
27:25
Reserved
RO
0h
24
IPx ACK* Counter Clear#/Enable
0 = Clears and holds IPx ACK* Counter at 0x0000h.
1 = Enables IPx ACK* Counter to count ACK*’s
R/W
0h
23:16
Reserved
RO
0h
15:0
IPx ACK* Count
Once enabled by setting IPx ACK* Counter
Clear#/Enable =1 provides a count of how many ACK*
have been returned by the IP in response to an ID, IO,
INT, or MEM cycle.
RO
0h
