Datex-Ohmeda Anesthesia Delivery Unit S/5, Technical Reference Manual

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Technical description A-ELEC
Document No. 8502856
D-15
Video interface palette
The video interface palette reads the digital display data from the frame memory and converts the
data into analogue RGB-signals. The synchronization signals for the conversion are generated by the
GSP.
The video interface palette is clocked by two pixel clocks. A 25 MHz clock is selected for VGA
resolution and a 40 MHz clock is selected for high resolution. The 40 MHz clock is internally converted
into a 80 MHz clock.
Graphics system processor (GSP)
There are four 16-bit registers in the GSP to which the host processor reads and to writes data.
Display controller resolution
The resolution of the display controller depends on initialization of the GSP's registers and frequency
of the video oscillator.
Reset signal
Reset signal comes from the digipower board through the mother board.
Monitor ID register
The monitor ID register contains a three bit (numeric values 0-7) monitor ID code. The register is
connected to pins 11-13 of the X3 D-connector. If no display is connected to the B-DISP board or if
the monitor ID code fails, 111 code is generated by pull-up resistors. If the ID code is 011 or 101, VGA
resolution is selected, otherwise high resolution is selected.
Figure 12 Display controller board B-DISP block diagram