Curtiss-Wright SCRAMNet+ SC150e, Hardware Reference Manual

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CSR DESCRIPTIONS
Copyright 2007 B-3 S SC150e HARDWARE REFERENCE
Bits Description
7 Enable Interrupt on Error - When this bit is set, Interrupt FIFO Full, Protocol Violation, Bad
Message and/or Receiver Overflow conditions causes an interrupt request.
8 Network Interrupt Enable - This bit must be set to transmit interrupt data to the network.
9 Override Transmit Interrupt Enable Flag - When this bit is set, an interrupt is sent out on the
network regardless of the status of the ACR Transmit Interrupt bit.
10
Enable Transmit Data Filter - When clear, the entire address space is not filtered and the node
is capable of transmitting all messages written to the node shared memory by the host on the
network. When set, the data-filter function is enabled for the address space above the first 4 K
bytes of SCRAMNet
+
memory. Bit 11 controls the lower 4 K bytes.
11 Enable Lower 4 K Bytes For Data Filter - When set, the lower 4 K bytes of address space is
data filtered if bit 10 is also set. When disabled, the address space will not be filtered.
12
Reset Receive/Transmit FIFO - This bit must be toggled from ‘0’ to ‘1’ and back to ‘0’ in order
to reset the Receive/Transmit FIFO. The R/T FIFO is a temporary high-speed holding area for
data flowing through the network.
NOTE : If the R/T FIFO were to be reset during active network transmissions, the data in the
FIFO at that time would be lost and it would cause errors on the downstream nodes in the
network ring.
13 Reset Interrupt FIFO - This bit must be toggled from ‘0’ to ‘1’ and back to ‘0’ to reset the
Interrupt FIFO.
14 Reset Transmit FIFO - This bit must be toggled from ‘0’ to ‘1’ and back to ‘0’ to reset the
Transmit FIFO.
15 Insert Node - This bit controls the nodes communications mode on the network as either a
receiver only or a receiver/transmitter. On power-up, this bit is OFF which translates to the
receiver-only mode. This allows user-written software (on each host processor on the network)
to be initiated from one node whenever the network is started cold. When this bit is ON, the node
is “inserted” into the network ring as a receiver/transmitter which is the normal operating mode if
the Fiber Optic Loopback CSR2[6] is disabled. This bit is invalid when the Enable Wire
Loopback CSR2[7] is ON.
*User access to Trigger 1 and Trigger 2 is not available on the PMC Card.