Curtiss-Wright SCRAMNet+ SC150e, Hardware Reference Manual

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CSR DESCRIPTIONS
Copyright 2007 B-2 S SC150e HARDWARE REFERENCE
Table B-1 CSR0 - General S SC150e Enable and Reset (Read/Write)
Bits Description
1-0 Network Communications Mode - Bit 0 controls the receive enable, and Bit 1 controls the
transmit enable.
00 None - In this mode, all communications between the node-shared memory and the
network is inhibited. The node is still able to pass network traffic but does not receive or
transmit any data. Loopback modes are also meaningless unless the Host to Shared
Memory Write bit is enabled.
01 Receive Only - In this mode, any received message is processed and written to node
shared memory. Data written by the host is placed in the node-shared memory and in the
Transmit FIFO but is not sent out on the network. In this mode, the Transmit FIFO will fill
and if the Error Interrupt is enabled, Transmit FIFO full interrupt will be triggered. Before
changing modes from Receive-Only to either Transmit-Only or Transmit/Receive, the
Transmit FIFO should be cleared. If not, all buffered transmit messages will be sent out on
the network.
10 Transmit Only - In this mode, any received message bypasses the shared memory and is
passed on. Any message written by the host to node-shared memory is transmitted on the
network. However, any received message is not written to node-shared memory.
(Transmissions are subject to data filter characteristics.)
11 Transmit/Receive - In this mode, any received message is processed, written to node
shared memory and passed on. Any message written by the host to node-shared memory
is transmitted on the network. This is the normal operation. (Transmissions are subject to
data filter characteristics.)
2 Redundant Transceiver Toggle - When this bit is cycled ‘0’, ‘1’, ‘0’, the optional redundant
transceiver selected link is changed.
3 Host Interrupt Enable - When this bit is set, a received message that is written to node shared
memory as an interrupt will generate an interrupt request, and the address will be written to the
Interrupt FIFO. This bit must be set in order to receive any interrupts from the network.
4 Auxiliary Control RAM Enable - When this bit is set, the ACR bytes are swapped in place of
the corresponding least-significant byte of every four-byte word in S memory. The
values written to those ACR byte locations dictate the type of interrupt that will occur when the 4-
byte memory location is written into. The ACR has five bits for interrupt control. They are as
follows:
ACR[0] - Receive Interrupt Enable - Setting this bit generates an interrupt to the host
for network interrupt data received in this location.
ACR[1] - Transmit Interrupt Enable - Setting this bit generates an interrupt to the
network for a host write to this shared memory location.
ACR[2] - External Trigger 1 - Setting this bit generates a trigger signal to an external
connector whenever there is a host write access to this shared memory location.*
ACR[3] - External Trigger 2 - Setting this bit generates a trigger signal to an external
connector whenever there is a network write to this shared memory location.*
ACR[4] - HIPRO location enable - Setting this bit causes the two 16-bit data or four 8-
bit items within the 32-bit address boundary to be transmitted as one 32-bit network
message. CSR2, bit 13 must also be set for this action to occur.
5
Interrupt On Memory Mask Match Enable - This bit must be set in order for any type of
memory interrupt to occur.
6 Override Receive Interrupt Enable Flag - When this bit is set, an interrupt is generated to the
host by any interrupt data received from the network regardless of the status of the ACR
Receive Interrupt bit.