Curtiss-Wright SCRAMNet+ SC150e, Hardware Reference Manual

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SCRAMNET OVERVIEW
Copyright 2007 2-8 S SC150e HARDWARE REFERENCE
INCOMING
INTERRUPT
CPU
INTERRUPT FIFO
ACR SHARED MEMORY
Address
Address
Data
Interrupt Bit
RING NETWORK
LOGIC
RING
CSR 4 CSR 5
A16 - A0 A22 - A16
A22 - A0
RIE D31 - D0
A22 - A0
D31 - D0
1
Figure 2-4 Incoming Interrupt
Error conditions are listed in CSR1 and are masked by setting the corresponding bit in
CSR9. If the Mask bits in CSR9 are all set to ‘1’, any error will generate an interrupt.
Otherwise, only errors with a ‘1’ in the appropriate Mask bit will generate an interrupt.
2.6.3 Forced Interrupt
The forced-interrupt method works the same for selected-interrupt except for the choice
of interrupt locations. All shared-memory locations are automatically set up to receive
and/or transmit interrupts depending on the ACR override conditions set in CSR0[6]
and/or CSR0[9].
When Override Receive Interrupt Enable CSR0[6] is set, an interrupt will be sent to the
host by any network-interrupt-data message , regardless of the status of the ACR Receive
Interrupt bit.
When Override Transmit Interrupt Enable CSR0[9] is set, an interrupt will be sent out on
the network regardless of the status of the ACR Transmit Interrupt bit.
A third condition, Receive Interrupt Override CSR8[10], is used to designate all
incoming network traffic as interrupt messages. The network message interrupt bit does
not need to be set.