Curtiss-Wright SCRAMNet+ SC150e, Hardware Reference Manual

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OPERATION
Copyright 2007 5-13 S SC150e HARDWARE REFERENCE
FORCED INTERRUPT
The forced-interrupt method works the same as the selected interrupt method with the
exception of choice of interrupt locations. All shared-memory locations are automatically
set up to receive and/or transmit interrupts depending upon the override bits set in CSR0
or CSR8.
MASKED OR SELECTED INTERRUPT
The masked- or selected-interrupt method requires choosing S SC150e
shared-memory locations on each node to receive and/or transmit interrupts. These
shared-memory locations may also be used to generate signals to external triggers. The
procedure for selecting shared-memory locations for interrupts and/or external triggers is
explained in paragraph 5.6: Auxiliary Control RAM.
CSR5 contains the Interrupt FIFO Not Empty CSR5[15]. Set CSR2[9,10] to enable self-
interrupts. This allows the message with the interrupt bit set to be processed as an
incoming network interrupt. CSR2[9] enables the node’s own message to be received as a
network message. CSR2[10] allows the interrupt bit to generate an interrupt if it is set.
SELF-INTERRUPTS
Set CSR2[10:9] to enable self-interrupts. This allows the message with the interrupt bit
set to be processed as an incoming network interrupt. CSR2[9] enables the node’s own
message to be received as a network message. CSR2[10] allows the interrupt bit to
generate an interrupt if it is set.
Receive Interrupt logic is described in Figure 5-3. If a native message is received and
Write Own Slot CSR2[9] is enabled, and Enable Interrupt on Receipt in Own Slot
CSR2[10] is set, the logic then checks for Receive Interrupt Enable. If Override Receive
Interrupt Enable CSR0[6] is set or Receive Interrupt Enable ACR[0] is set, and if
Interrupt on Memory Mask Match Enable CSR0[5] is set, the address is placed on the
Interrupt FIFO.
NOTE
: Interrupt data is not filtered when the data filter is enabled.