Curtiss-Wright SCRAMNet+ SC150e, Hardware Reference Manual

Page: 58 / 140

OPERATION
Copyright 2007 5-8 S SC150e HARDWARE REFERENCE
5.5.4 Throughput
A maximum throughput of 6.5 MB/sec could be achieved if only one node were
transmitting data, assuming the host CPU could offer the data at that rate. When more
than one node is transmitting in BURST mode, then the effective output per node is 6.5
MB/sec divided by the number of transmitting nodes. In BURST and BURST PLUS
modes, the node never retransmits its own messages.
In the BURST PLUS mode, a 256-byte packet provides 16.2 MB/s of data throughput. A
1024-byte packet provides 16.7 MB/s maximum data throughput.
When multiple nodes are transmitting in the BURST mode, the network data passing
through the other nodes can affect that node’s output performance. If a node’s receiver is
so busy that the Transceiver FIFO is never empty, and the node has already sent a
message, then the node will have to wait before it can send another message of its own
until either one of its messages comes back or the timer runs out. When the node’s own
message is received, it is not placed in the Transceiver FIFO thereby creating an
opportunity for the node to send a message from the Transmit FIFO.
In PLATINUM and PLATINUM PLUS modes, error detection is enabled. This will
affect node latency in that some messages must be retransmitted.
NETWORK TIME-OUT
Reset the transmit time-out according to the mode of operation selected by writing a 16-
bit non-zero value to CSR5 as described in subsection 4.8.4.
5.6 Auxiliary Control RAM
The ACR is a 5-bit register. When ACR Enable CSR0[4] is set, shared memory is not
accessible by the host, and the ACR byte is viewed as the least significant byte of every
shared-memory four-byte address. The ACR byte value controls the interrupt action(s)
taken whenever a write occurs to any byte of the shared-memory four-byte word. Table
5-2 describes the ACR functions.
Table 5-2 ACR Functions
Bit Function
0 Receive Interrupt Enable (RIE)
1 Transmit Interrupt Enable (TIE)
2 External Trigger 1
3 External Trigger 2
4 HIPRO Location Enable
If these ACR actions are disabled, then no action will be taken when an interrupt
condition exists unless override bits CSR0[6] or CSR8[10] are set.
The interrupt action and/or HIPRO
mode for a particular shared-memory location is
defined by setting these bits. Once the ACR has been defined, set the ACR Enable bit
CSR0[4] back to zero so that shared-memory can again be accessed. The ACR actions are
still in effect, but the ACR bytes can no longer be accessed while the ACR Enable bit is
zero.