SPECIFICATIONS
Copyright 2007
A-5
S SC150e HARDWARE REFERENCE
A.3 SC150e CPCI
A.3.1 Hardware Specifications
Hardware Compatibility: ..................................... PCI local bus specification, rev. 2.1,
CompactPCI Core Specification,
PICMG 2.0 R3.0, and CompactPCI Hot
Swap Specification, PICMG 2.1 R1.0.
Physical Dimensions:...........................................6.299” x 3.937”
Weight: ................................................................0.354 lb. (w/4 MB memory)
Electrical Requirements:...................................... +4.75 to +5.25 VDC, 1.5 Amps max.
PCI Signaling Levels ........................................... Universal (+5.0 V and +3.3 V support)
Temperature Range
Storage: ......................................................-40
°
to +70
°
C
Operation:...................................................0
°
to +60
°
C
Humidity Range:
Storage .......................................................0%
to
95% (noncondensing)
Operating....................................................10%
to
90% (noncondensing)
Network Line Transmission Rate: .......................150 million bits/second
Message Length:
Fixed Length: .............................................82 Bits
Variable Length: ........................................46 bits + 256 or 1024 Data Bytes
Maximum
Maximum Nodes on Network Ring:....................256
Error Correction:.................................................. Available in PLATINUM mode only
Maximum Node Separation:
Standard Fiber:...........................................300 meters
Long Link Fiber .........................................3500 meters*
Factory installed memory options:............. 2 MB, 4 MB, or 8 MB
Effective Per-Node Bandwidth:
4 bytes/packet: ........................................... 6.5 MB/sec
256
bytes/packet:
....................................... 16.2
MB/sec
1024 bytes/packet:...................................... 16.7 MB/sec
Node Latency:
4 bytes/packet: ...........................................250 ns -800 ns
256 bytes/packet: .......................................250 ns - 16 µs
1024 bytes/packet:......................................250 ns - 61.8 µs
Mean Time Between Failures (MTBF)**
2 MB Memory............................................187,887 hours
4 MB Memory............................................187,740 hours
8 MB Memory............................................185,809 hours
Internal clock speeds:
S SC150e board crystal ..........150 MHz, +/-100 ppm
1
26.66 ns timer is a divide-by-four:.............37.5 MHz
2
1.706
μ
s timer is a divide-by-256: .............585.9 KHz
3
1.
Specifications on the crystal demonstrate the precision and stability of the main clock from which all other
clocks are derived. This does not include the vagaries introduced by the circuit.
2.
The 37.5 MHz clock is the distributed (on board) clock used by other circuits on SCRAMNet host cards.
3.
The 585.9 KHz clock is counted by the internal (to ASIC) users’ timer.
*
Contact Curtiss-Wright Controls, Inc., regarding availability of SC150e card options
** The MTBF numbers are based on calculations using MIL-HDBK-217F, Appendix A, for a ground-
benign environment.
Summary of Contents for SCRAMNet+ SC150e
Page 2: ......
Page 79: ...OPERATION Copyright 2007 5 29 SCRAMNet SC150e HARDWARE REFERENCE Figure 5 10 Quad Switch ...
Page 82: ......
Page 94: ......
Page 108: ......
Page 121: ...D D CONFIGURATION AIDS APPENDIX D CONFIGURATION AIDS ...
Page 122: ......
Page 127: ...1 GLOSSARY GLOSSARY ...
Page 128: ......
Page 135: ...1 INDEX INDEX ...
Page 136: ......