Curtiss-Wright SCRAMNet+ SC150e, Hardware Reference Manual

Page: 85 / 140

SPECIFICATIONS
Copyright 2007 A-3 S SC150e HARDWARE REFERENCE
A.2 SC150e PMC
A.2.1 Hardware Specifications
Hardware Compatibility: ..................................... PCI local bus specification, rev. 2.1
Draft standard for a common mezzanine
card family: CMC (IEEE P1386/Draft
2.0)
Draft standard physical and
environmental layers for PCI Mezzanine
cards: PMC (IEEE P1386/Draft 2.0)
Physical Dimensions:...........................................2.91" x 5.86"
Weight: ................................................................0.24 lb. (w/4 MB memory)
Electrical Requirements:...................................... +4.75 to +5.25 VDC, 1.5 Amps max.
PCI Signaling Levels ........................................... Universal (+5.0 V and +3.3 V Support)
Temperature Range
Storage: ......................................................-40
°
to +70
°
C
Operation:...................................................0
°
to +60
°
C
Humidity Range:
Storage .......................................................0%
to 95% (noncondensing)
Operating....................................................10% to 90% (noncondensing)
Network Line Transmission Rate: .......................150 million bits/second
Message Length:
Fixed Length: .............................................82 Bits
Variable Length: ........................................46 bits + 256 or 1024 Data Bytes
Maximum
Maximum Nodes on Network Ring:....................256
Error Correction:.................................................. Available in PLATINUM mode only
Maximum Node Separation:
Standard Fiber:...........................................300 meters
Long Link Fiber .........................................3500 meters
Factory installed memory options:............. 2 MB, 4 MB or 8 MB
Effective Per-Node Bandwidth:
4 bytes/packet: ........................................... 6.5 MB/sec
256 bytes/packet: ....................................... 16.2 MB/sec
1024 bytes/packet:...................................... 16.7 MB/sec
Node Latency:
4 bytes/packet: ...........................................250 ns -800 ns
256 bytes/packet: .......................................250 ns - 16 µs
1024 bytes/packet:......................................250 ns - 61.8 µs
Mean Time Between Failures (MTBF)*
2 MB Memory............................................225,361 hours
4 MB Memory............................................217,276 hours
8 MB Memory............................................189,130 hours
Internal clock speeds:
S SC150e Card crystal............150 MHz, +/-100 ppm
1
26.66 ns timer is a divide-by-four:.............37.5 MHz
2
1.706
μ
s timer is a divide-by-256: .............585.9 KHz
3
1. Specifications on the crystal demonstrate the precision and stability of the main clock from
which all other clocks are derived. This does not include the vagaries introduced by the circuit.
2. The 37.5 MHz clock is the distributed (on Card) clock used by other circuits on SCRAMNet
host cards.
3. The 585.9 KHz clock is counted by the internal (to ASIC) users timer.
* The MTBF numbers are based on calculations using MIL-HDBK-217F, Appendix A, for a ground-
benign environment.