Curtiss-Wright SCRAMNet+ SC150e, Hardware Reference Manual

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CSR DESCRIPTIONS
Copyright 2007 B-10 S SC150e HARDWARE REFERENCE
Table B-10 CSR9 - S SC150e Interrupt On-Error Mask*
Bits Description
0 Transmit FIFO Full Mask
1 Transmit FIFO not Empty Mask
2 Transmit FIFO 7/8 Full Mask
3 Built In Self Test Stream (BIST) - Internal 82-bit BIST shift register output.
4 Interrupt FIFO Full Mask
5 Protocol Violation Mask
6 Carrier Detect Fail Mask
7 Bad Message Mask
8 Receiver Overflow Mask
9 Transmitter Retry Mask
10 Transmitter Retry Due to Time Out Mask
11 Redundant TX/RX Fault Mask
12 Interrupt on General Purpose Counter/Timer Overflow Mask
13 See Below
14 See Below
15 Fiber Optic Bypass Switch Not Connected Mask
General Purpose Counter/Timer Modes
CSR8[9] CSR9[14] CSR9[13] Counter/Timer Modes
0 0 0 Count Errors
0 0 1 Count Trigs (1&2)
0 1 0 Transit Time
0 1 1 Network Events
1 1 X Free Run @ 26.66 ns
1 0 1 1.706 µs w/trig 2 CLR
* To enable an On-Error mask, set the bit to ‘1’.
Table B-11 CSR10 - DEC_IGNORE
Bits Description
0 1 = Non-DEC system (Factory default)
0 = DEC system
NOTE : This CSR is shadowed in the controller state machine so that its value, when written,
can be read from CSR10.
15-1
Reserved (always 0)