Curtiss-Wright SCRAMNet+ SC150e, Hardware Reference Manual

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GLOSSARY
Copyright 2007 Glossary 1 S SC150e HARDWARE REFERENCE
A16
----------------------------------A type of module that provides or decodes an address on address lines
A01 through A15.
A24
----------------------------------A type of module that provides or decodes an address on address lines
A01 through A23.
A32
----------------------------------A type of module that provides or decodes and address on address lines
A01 through A31.
ACR
--------------------------------auxiliary control RAM. A memory buffer typically used as a data bus
width extension for control purposes only. Also referred to as shadow
memory.
address-only cycle
---------------A DTB cycle that consists of an address broadcast, but no data transfer.
The slave does not acknowledge address-only cycles and the master
terminates the cycle without waiting for an acknowledgment.
alarm
-------------------------------Manually resetable latched error condition.
bad message
-----------------------A message error condition reported by a node’s receiver circuitry. This
condition is automatically corrected by S hardware.
block read cycle
------------------A DTB cycle used to transfer a block of 1 to 256 bytes from a slave to a
master. This transfer is done using a string of 1-, 2-, or 4-byte data
transfers. Once the block transfer is started, the master does not release
the DTB until all of the bytes have been transferred. It differs from a
string of read cycles in that the master broadcasts only one address and
address modifier (at the beginning of the cycle.) Then the slave
increments this address on each transfer so that the data for the next
cycle is retrieved from the next higher location.
block write cycle
-----------------A DTB cycle used to transfer a block of 1 to 256 bytes from a master to a
slave. The block write cycle is very similar to the block read cycle. It
uses a string of 1-, 2-, or 4-byte data transfers and the master does not
release the DTB until all of the bytes have been transferred. It differs
from a string of write cycles in that the master broadcasts only one
address and address modifier (at the beginning of the cycle). Then the
slave increments this address on each transfer so that the next transfer is
stored in the next higher location.
board
-------------------------------A printed circuit board (PCB), its collection of electronic components,
and either one or two 96-pin connectors that can be plugged into the
backplane connectors.
broken ring------------------------
If any of the nodes in a fiber-optic ring loses the ability to retransmit an
incoming message, then the ring is “broken.”
BURST
-----------------------------A protocol where messages are transmitted without error correction to
gain higher throughput.
BURST+
---------------------------Also BURST PLUS. A variable-length message packet size enhancement
for the burst protocol. Maximum packet size may be set to either 256
bytes or 1024 bytes plus a 46-bit header.
bus timer
---------------------------A functional module that measures the time each data transfer takes on
the DTB and terminates the DTB cycle if a transfer takes too long.
Without this module, it could wait forever for a slave to respond if the
master tries to transfer data to or from a nonexistent slave location. The
bus timer prevents this by terminating the cycle.