Curtiss-Wright SCRAMNet+ SC150e, Hardware Reference Manual

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OPERATION
Copyright 2007 5-7 S SC150e HARDWARE REFERENCE
ERROR CORRECTION
Error correction is the automatic retransmission of a SCRAMNet Network message when
the original message is received in error by the originating node. The message will be
retransmitted indefinitely until it is received correctly. During transmit retry, the same
message is being sent. This prevents any new messages from being transmitted by this
node. The transmit FIFO will hold these new messages until the retry message is received
correctly.
If the original message is received by the originating node with some type of bit error,
then this results in the transmit retry bit in CSR1 being set. If the original message is not
received by the originating node in the time-out period specified in CSR5, then this
results in the transmit retry time-out bit in CSR1 being set. The time-out period is based
on the number of nodes in the network ring and the total length of cable used.
5.5.3 Performance
NODE LATENCY
Node latency is an important factor in networked application in real-time systems design.
Data transfer around the network, while fast, does have a measurable delay.
Node latency can be defined as the time delay at a node before a foreign message can be
retransmitted. This delay is a minimum of 247 ns—the time to transmit one byte. The
maximum node latency depends on the maximum message size and could be from 800 ns
to 61.8 µs, depending on the message length selection. To approximate the total
maximum delay on the network, multiply the maximum node latency by the number of
nodes in the system, and add a propagation delay of 5 ns/meter multiplied by the total
message path of the ring in meters.
DATA TRANSFER
While the S SC150e Network appears as a shared-memory system, it is still a
data network. The S SC150e Network includes a series of FIFO buffers to
collect data changes until they are transmitted to the other nodes. The Transmit FIFO and
the Interrupt FIFO are both 1024 messages in length. These numbers may become
significant when performing data transfers of large blocks of data in a short period of
time.
HOLDOFF
If the Transmit FIFO becomes full, subsequent read or write cycles to S
SC150e memory will be extended until the Transmit FIFO is no longer full (see
subsection 5.11.4 for more information).
SHARED-MEMORY WRITE
S SC150e shared-memory is based upon a 32-bit word. If an 8- or 16-bit
write occurs from the host system, then the 32-bit word that contains that 8- or 16-bit
write is sent on the network. Therefore, it is important that other nodes do not
simultaneously modify other 8- or 16-bit segments within that 32-bit word.