Curtiss-Wright SCRAMNet+ SC150e, Hardware Reference Manual

Page: 68 / 140

OPERATION
Copyright 2007 5-18 S SC150e HARDWARE REFERENCE
5.10 General Purpose Counter/Timer
This 16-bit counter/timer is programmed by changing CSR9[13] and CSR9[14] to select
the desired mode as described in Table 5-5. CSR8[9] can be set to override the
counter/timer mode settings and allow the counter/timer to run free at 26.66 ns
(37.5 MHz). CSR9[12] can be set to generate an interrupt upon overflow of the
counter/timer. The output from the event counter/timer is stored in CSR13. See Appendix
B, page B-4, B-9, B-10, and B-12 for more information.
5.10.1 Available Modes
The General Purpose Counter/Timer register (CSR13) can be used as a counter or a
timer. The mode is selected via a combination of registers and bits that are explained on
page B-10. Table 5-5 describes the counter/timer modes available:
Table 5-5 General Purpose Counter/Timer Modes
Mode Description
Count Errors: Each error detected in CSR1 will increment the counter by 1.
Count Trigger 1 and 2: Each time a trigger event occurs the counter will increment.
Transit Time:
Set this mode and clear the counter. The counter will begin counting
when the next message is transmitted, and stop counting when any
message generated by this node is received.
Network Events: Count incoming network messages.
Free Run @ 26.66 ns: Increment counter using internal 37.5 MHz clock. Counter will roll
over every 1.78 ms.
Free Run @ 1.706
μ
s with
Trigger 2 to CLEAR:
Increment counter using the 585.9 KHz clock. Counter will roll over
every 111.8 ms. Assertion of Trigger 2 will clear the counter.
5.10.2 Rollover/Reset
A rollover/reset can generate an interrupt by setting Interrupt On General Purpose
Counter/Timer Overflow Mask CSR9[12]. When this bit is set, an interrupt is generated
to the host system whenever the counter register (CSR 13) rolls over or overflows.
Interrupt On Errors CSR0[7] mode must be enabled in order for this to work properly.
The counter/timer will roll over when it reaches 65,535 + 1.
Only one mode may be selected at a time since they use the same counter/timer register
(CSR13) for output.
5.10.3 Presetting Values
The counter/timer register counts upward and may be preset with a value to arrive at the
desired interrupt interval.