Curtiss-Wright SCRAMNet+ SC150e, Hardware Reference Manual

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CSR DESCRIPTIONS
Copyright 2007 B-4 S SC150e HARDWARE REFERENCE
Table B-2 CSR1 - S SC150e Error Indicators (Read Only with Write/Reset for interrupts)
NOTE
: Reading CSR1 will reset the latched error conditions by clearing bits 0, 2, 4, 5,
6, 7, 8, 9, 10, 11, 12, and 13.
Bit Description
0 Transmit FIFO Full (Latched) - When this bit is set, the Transmit-FIFO-Full condition exists.
This occurs when there is more data coming from the host to the network than the network can
absorb. When the shared memory is full, host writes will be held off by the S
SC150e host interface logic until the Transmit FIFO is no longer full.
1 Transmit FIFO Not Empty - This bit does not represent any type of error condition, but rather
just a report on the state of the Transmit FIFO. A ‘0’ represents an empty FIFO, where a ‘1’
indicates at least one message in the FIFO.
2 Transmit FIFO 7/8 Full (Latched) - This bit indicates that the Transmit FIFO is 7/8 full. A ‘0’
represents a FIFO that is less than 7/8 full, where a ‘1’ indicates the FIFO is backing up and is
more than 7/8 full.
3 Always 0
4 Interrupt FIFO Full (Latched) - When this bit is set, the Interrupt FIFO Full error condition
exists. Reset the Interrupt FIFO by toggling CSR0[13] to ON then to OFF.
5 Protocol Violation (Latched) - When this bit is ON, there has been a signal error at the
physical layer (fiber or coaxial) resulting from noise on the transmission lines or a result of
hardware failure. It can be any one of the following: Missing transition for two clock periods on
either line, Parity error or a Framing error.
6
Carrier Detect (Latched) - This bit is set if the receivers do not detect any or enough output
from the previous nodes transmitters. This is usually an indication that the fiber optic lines have
become disconnected or there may be dust/dirt where the fiber optic connections have been
made. A visual inspection of the network lines will need to be made.
7 Bad Message (Latched) - When this bit is set, the hardware has detected an error in the
message packet received on the network. If this error persists, it is an indication that a
hardware problem on the SCRAMNet
+
Card may exist.
8 Receiver Overflow (Latched) - When this bit is set, the Receive FIFO has received more data
than the node is able to process. This condition may indicate a hardware problem on the Card.
9 Transmit Retry (Latched) - This bit is set if a message returns to the originating node with bit
errors. The message is automatically retransmitted indefinitely until it returns without bit errors.
This is considered to be an error condition.
10 Transmit Retry Time-out (Latched) - This bit is set if a message does not return to the
originating node within the time-out value specified in CSR5. The message is automatically
retransmitted indefinitely until it returns. This is considered to be an error condition.
11 Redundant Transmit/Receive Fault (Latched) - This bit is set if the currently selected optional
redundant transceiver has faulted and reverted to the other link. The default value is ‘0’
12 General Purpose Counter/Timer Overflow (Latched) - This bit toggles a 16-bit counter/timer.
The events to be counted/timed are set using CSR8[9]; CSR9[13]; and CSR9[14]. The output is
held in CSR13. The counter/timer can: count errors, count trigger events for triggers 1 and 2,
transmit time, network events, free run @ 26.66 ns, and free run @ 1.706 ns with trigger 2
CLEAR.