CMT2380F64
www. cmostek. com
Rev 0.3 | 1 / 83
MCU Features
◼
A 32-bit general-purpose micro-controller based on the Arm® Cortex®-M0 core
，
Single cycle hardware
multiply instruction
◼
Up to 64 KByte on-chip Flash
- supports encrypted storage and hardware ECC verification
- Endurance more than 100,000 cycles, 10 years of data retention
◼
8 KByte on-chip SRAM
，
supports hardware parity
◼
Programming method
：
- SWD online debugging interface
- UART Bootloader
◼
23 / 29 general IO (4 with SPI multiplexing in RF part)
◼
Low-power management
：
- Stop mode: RTC Runs, maximum 8 KByte SRAM retention, CPU register retention, all IO retention
- Power Down mode (PD): supports 3 IO wakeup
◼
Clock
：
Up to 48 MHz
- HSE
：
4 MHz~20 MHz
，
external high-speed crystal
- LSE
：
32.768 KHz
，
external low-speed crystal
- HSI
：
Internal high-speed RC OSC 8 MHz
- LSI
：
Internal low-speed RC OSC 30 kHz
- Built-in high-speed PLL
- One channel clock output, which can be configured as configurable system clock, HSE, HSI or PLL
post-divided output
◼
Reset
- Supports power-on/power-down/external pin reset
- Supports programmable low voltage detection and reset
- Supports watchdog reset
◼
Communication Interface
- 3xUART interface, with a maximum rate of 3 Mbps, of which 2 USART interfaces support 1xISO7816 , 1xIrDA,
LIN,1 of which supports low power consumption (LPUART
）
, the highest communication rate in this mode is
9600bps and stop mode can be awakened.
- 2xSPI, the rate is up to 18 MHz, one of which supports multiplexing with I2S
- 2xI2C, the rate is up to 1 MHz, master-slave mode is configurable, and dual-address response is supported
in slave mode
◼
Analog interface
-1x12 bit high-speed ADC, 1 Msps, up to 6 external single-ended input channels
-1xOPAMP, built-in programmable gain amplifier up to 32 times
-1xCOMP, built-in 64-level adjustable comparison benchmark
-1x high speed 5-channel DMA control, source address and destination address can be configured
CMT2380F64
Ultra-low Power Sub-1GHz Wireless Transceiver
SoC
