Plexus 9000 Planning and Engineering Guide
Quad OC12 Network Access Module
Section 130-120-750
Issue 2, May 28, 2004
Telica, Inc.
5-181
5.16.3.6
Microprocessor, Memory Bus Controller and Memory
The processor section has a microprocessor with memory, a
microprocessor controller, which provides interfaces between the
microprocessor, memory, MLBA and SAR for controlling the module.
Each module also has an EEPROM that contains the CLEI code for the
module.
5.16.3.7
Segmentation and Reassembly (SAR)
There is a stand-alone Segmentation and Reassembly (SAR) unit on the
PCI bus of each module to provide the microprocessor a means of
communication to the SF module.
5.16.3.8 Power
Each ATM Network Access module has its own DC-to-DC converter (not
shown), which converts the 48 volts supplied from the backplane to the
local voltages required (5Vdc, 3Vdc, etc.).
5.16.3.9
Clocks and Synchronization
Clock and framing information is received from the System Timing
module located on the SP. The clock control circuitry of the IOM
distributes these on the module.