Plexus 9000 Planning and Engineering Guide
Octal DS3/STS-1 I/O Front Module
Section 130-120-600
Issue 4, March 26, 2004
Telica, Inc.
5-153
5.13.3 Theory
of
Operation
Each Octal DS-3/STS-1 IOM has 8 DS-3 or STS-1 interfaces that are
controlled by a microprocessor. In the transmit direction the DS-3s or
STS-1s enter the interfaces from the rear module. Each interface
demultiplexes the DS-3 or STS-1 into seven VT groups of 4 DS1s or
VT1.5s that pass to the TSU circuitry. In the TSU, the signals are
converted to ATM cells that are sent to the Parallel In/Serial Out Interface
where they are converted from parallel to serial. The serial data is sent to
the SF module for switching.
Refer to
for a block diagram of the IOM.
The 89-0411 and 89-0425 IOMs have digital signal processor (DSP)
circuitry on a daughter card for use during DTMF digit collection.
To/From
Rear
Card
To/From
System
Processor/
Switch
Fabric
To/From
Switch
Fabric
MID PLANE
Clock
Control
PCI BRIDGE
MLBA
SAR
TSU
RAM
RAM
FSU
E
E
P
R
O
M
Parallel
serial
Interface
P412-AA
03-30-04
OCTAL DS3 STS-1 IOM front
LIU/Super mapper
Processor
HDLC
LATCH
SDRAM
Memory
Buffers
L2
Cache
XCVR
FLASH
Memory
Connector
FPGA
DSP
REG
Figure 5.13-2. Octal DS-3/STS-1 IOM Block Diagram