27
AT40K Series Configuration
1009B–FPGA–03/02
Figure 12.
Slave Serial Start of Configuration
Notes:
1. INIT is an open drain pin during configuration downloads, this pin must be driven by only an open drain driver. The pull-up
value should be properly chosen to allow the pin to be pulled High prior to the first rising edge of CCLK. Failure to do so will
not cause the part to abort the download, but may cause the user confusion if the FPGA does drive the pin Low.
2. For configuration interface inputs, t
DCI
indicates the time for the user I/O to tri-state.
3. The pins CSOUT and CHECK are claimed by the configuration interface only if enabled by the control register. Both are
enabled by default after power-on-reset or manual reset.
4. Users must drive CON Low for 3 rising edges of CCLK, and then should release it.
USER MAY RELEASE
DRIVEN BY USE ONLY
D0
t
PCCLK
USER I/O
USER I/O
USER I/O
t
DCI
(2)
USER I/O
USER I/O
t
SCCCLK
20K PULL-UP
(INTERNAL)
t
SCC
USER I/O
t
SCD
t
HCD
BIT 0
BIT 1
BIT 2
10K PULL-UP
(INTERNAL)
CCLK
CON
(4)
INIT
(1)
CHECK
(3)
CSOUT
(3)
LDC
HDC
