14
AT40K Series Configuration
1009B–FPGA–03/02
From the power-on-reset, manual reset, or the configuration idle state, when CON and
the appropriate chip select (CS
0
or CS
1
) is activated, the device begins clocking data.
For AT40K series devices, the timing relationships are fixed, and no additional data is
allowed at the front of the bitstreams. Serial data is read in the most-significant-bit first.
The null byte is read in, followed by the preamble. If the expected preamble value is not
seen as the second byte of data, an error is reported by driving INIT Low and terminat-
ing the configuration download.
After the preamble check, the state machine loads the configuration control register,
which controls various features of the configuration process.
Small areas of the AT40K arrays can be programmed independently of each other.
Each of these areas is known as a window. After the control register, the device loads
the number of configuration windows. A single bitstream can have up to 64K windows.
The minimum data block size for a window is 1 word.
Next, the start and end addresses of the first window are loaded. An invalid start
address will cause an error; the INIT pin is driven Low, and the configuration download
is terminated.
Next, data is loaded into the configuration SRAM (unless the CHECK function is
activated).
Table 6.
Sample 8-bit wide stream
msb<>lsb
00000000
null
10110111
preamble
00000000
control register byte 0
00000000
control register byte 1
00000000
control register byte 2
00000000
control register byte 3
00000000
number of windows, msb
00000001
number of windows, lsb
00000000
start address 0
00000000
start address 1
00000000
start address 2
00000000
end address 0
00000000
end address 1
00000011
end address 2
11110000
data, byte 0
11100001
data, byte 1
11010010
data, byte 2
11000011
data, byte 3
11100111
postamble
