7
AT40K Series Configuration
1009B–FPGA–03/02
Figure 1.
Dual-use IO
Configuration States
When power is first applied to an AT40K series FPGA, an internal power-on-reset circuit
senses VDD and activates at approximately 2.1V. The FPGA then enters the power-on-
reset state. During this state, INIT is driven Low, CON is driven Low, LDC is driven Low,
HDC is driven High, and all user I/O are tri-stated. I/O thresholds, pull-ups and put-
downs are at an indeterminate state. The FPGA configuration clear cycle begins and the
configuration SRAM is reset. The configuration clear cycle is repeated a nominal 150 ms
to allow VDD to rise to the minimum operational level for the device (3.0V).
This additional delay is only applied at power-on-reset, and is not needed for manual
reset.
Once the configuration clear cycle is complete, RESET is sampled. If High, INIT is
released. This open drain pin is sampled to make sure all other devices (if any) in a cas-
cade chain are also done with the configuration clear cycle. Once INIT goes High the
mode pins are sampled.
If Mode 0 is detected, the part proceeds to the configuration download state. CON is
held Low by the FPGA, HDC remains High, LDC remains Low, and CCLK is now driven
by the FPGA at a nominal frequency of approximately 1 MHz. The appropriate configu-
ration interface pins for Mode 0 become active.
If a slave mode is detected (i.e., Modes 1, 2, 6, or 7), then CON is released and pulled
High with the internal pull-up resistor. Once CON goes High, the part proceeds to the
idle state and LDC and HDC are released. The internal oscillator stops running. The part
is now available for configuration download.
When RESET is lowered, the manual reset state is entered. An internal oscillator begins
running, INIT, CON and LDC are driven Low, and HDC is driven High. During this state,
the FPGA configuration clear cycle begins and the configuration SRAM is reset. Once
this cycle is complete, RESET is sampled and the reset state machine proceeds as
above. The configuration reset state diagram is shown in Figure 2
To user logic
To configuration logic
From user logic
From Configuration
Configuration claim
From user logic
From configuration
