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AT40K Series Configuration
1009B–FPGA–03/02
Master Mode
The Master Mode is auto-configuring; that is, after power-on-reset (POR) and the clear-
ing of configuration memory, it self-initiates configuration. The Master Mode uses an
internal oscillator to provide CCLK for clocking the external EEPROMs (configurators)
which contain the configuration data. CCLK also drives the downstream devices
(Slaves) in the configuration cascade chain. Master Serial Mode clocks and receives
data from an EEPROM Serial Configuration Memory (AT17C65, AT17C128, AT17C256,
AT17C512, AT17C010). After auto-configuration is complete, re-configuration can be
initiated manually by the user.
Slave Modes
In slave modes, configuration is always initiated by an external signal. Data is applied to
the device on the rising edge of CCLK. In Slave Serial Mode, the device receives serial
configuration data. In Slave Parallel Mode, the device receives either 8-bit wide or 16-bit
wide parallel data. In Slave Parallel Up Mode, the device receives either 8-bit or 16-bit
wide parallel data and generates a 20-bit address up counter for use in addressing
memories. CCLK is not generated in slave modes.
Synchronous RAM Mode
In Synchronous RAM Mode, the device receives a 32- or 40-bit wide bitstream com-
posed of a 24-bit address and either an 8-bit wide or 16-bit wide word of data. Address,
data and write enable are applied simultaneously at the rising edge of CCLK. In this
mode, designed to interface to a generic IO port of a microprocessor, the FPGA config-
uration SRAM is seen as a simple memory-mapped address space. The user has full
read and write access to the entire FPGA configuration SRAM. The overhead normally
associated with bitstreams is eliminated, resulting in faster re-configuration.
Configuration Pins
During configuration, the flow of design data to and from the device is controlled by the
dedicated mode pins and a number of dual-function pins that double as user I/O under
normal programmed operation. The number of dual-function pins required for each
mode varies, see Table 2.
