19
AT40K Series Configuration
1009B–FPGA–03/02
Figure 4.
System Level Integration: Start of Configuration
Notes:
1. The appropriate global and fast clock nets are disabled on the first rising edge of the associated global or fast clock input sig-
nal after CON is driven Low. The nets are forced High for glitch less suppression of activity.
2. User I/O are tri-stated on the first rising edge of CCLK after CON has been driven Low.=
CCLK
CON
GLOBAL SET/
RESET NET
(2)
t
DGSR
GCLK
(1)
,FCLK
(1)
t
SGF
USER CONTROL
t
DCGTS
INTERNAL CLOCK NET
USER CONTROL
(OPTIONALLY TRISTATED DURING CONFIGURATION)
(OPTIONALLY FORCED ON (LOW) DURING CONFIGURATION)
(OPTIONALLY DISABLED DURING CONFIGURATION)
t
HGF
t
SCC
10K PULL-UP
1
