30
AT40K Series Configuration
1009B–FPGA–03/02
Mode 7: Slave Serial
Figure 15.
Stand-alone 7 Microprocessor System Application
A Mode 7 Slave Serial device is usually configured in a system whereby data comes
either from a serial EEPROM or from the data port of a microprocessor. Figure 15
shows a typical system application with a microprocessor.
In Mode 7, CCLK is driven by an external device, most often either a microprocessor or
a Master Serial FPGA, in cascade mode. Like the Master Serial device, serial data is
driven into the D
0
pin of the FPGA. To begin configuration, CON must be driven Low.
Once the bitstream is completed, CON is released by the FPGA, indicating the device is
completely ready for user operation. Configuration time depends on the frequency of the
external clock driving CCLK. The maximum frequency in which a Mode 7 device can be
downloaded is 33 MHz. A full bitstream for the AT40K20 can be downloaded in only 4.6
ms (30 ns per bit of configuration data).
Configuration Data Source:
Serial EEPROM,
Microprocessor
Dedicated Configuration Pins:
RESET, CON, M
0
, M
1
, M
2
,
CCLK
Dual-use I/O:
D
0
, INIT, LDC, HDC
Optional Dual-use I/O:
CSOUT, CHECK
M0
M1
M2
OTS
CHECK
CCLK
D<0>
RESET
INIT
CON
CSOUT
AT40K
VDD
Optional IO
Optional IO
IO<0>
IO<1>
IO<2>
IO<3>
IO<4>
IO<5>
IO<6>
IO<7>
IO<8>
IO<9>
IO<10>
IO<11>
IO<12>
IO<13>
IO<14>
IO<15>
IO<16>
IO<17>
IO<18>
IO<20>
IO<21>
IO<22>
IO<23>
IO<24>
IO<19>
IO<25>
IO<26>
IO<27>
IO<28>
IO<29>
IO<30>
IO<31>
Microprocessor
Reset
CLK
RESET
CLOCK
