11
AT40K Series Configuration
1009B–FPGA–03/02
CR
4
:
0 = Memory Lockout disabled
1 = Memory Lockout enabled
CR
4
is the Security Flag and controls the writing and checking of configuration memory
during any subsequent configuration download. When CR
4
is set, any subsequent con-
figuration download initiated by the user, whether a normal download or a CHECK
function download, causes the INIT pin to immediately activate. CON is released, and
no further configuration activity takes place. The download sequence during which CR
4
is set is NOT affected. The Control Register write is also prohibited, so bit CR
4
may only
be cleared by a power-on-reset or manual reset.
CR
5
:
Not used (ignored)
CR
6
:
0 = OTS disabled
1 = OTS enabled
Setting CR
6
makes the OTS pin an input which controls the global tri-state control for all
user I/O.
CR
7
:
0 = 8-bit data access
1 = 16-bit (Wide) data access
CR
7
is the Wide data control bit. Setting this bit immediately enables bits D
8
:D
15
of the
configuration interface as inputs for all parallel modes (2 and 6). All writes and checks of
configuration memory are subsequently performed by 16 bits. Cr
7
is ignored in serial
modes (0, 1 and 7).
CR
8
:
Not used
(ignored)
CR
9
:
Not used
(ignored)
CR
10
:
Not used
(ignored)
CR
11
:
Not used
(ignored)
CR
12
:
Not used
(ignored)
CR
13
:
0 = CCLK normal operation
1 = CCLK continues after configuration
Setting bit CR
13
allows the CCLK pin to continue to run after configuration download is
completed. This bit is valid for Master Mode.
CR
14
:CR
15
:
00 = 1 MHz
01 = 2 MHz
10 = 4 MHz
11 = 8 MHz
Bits CR
14
and CR
15
speed up the internal oscillator and allow the Master Mode to drive
CCLK at 1, 2, 4 or 8 MHz. Setting these bits immediately enables the higher CCLK
frequency.
