17
AT40K Series Configuration
1009B–FPGA–03/02
Checksum Function
The AT40K family supports a Checksum Function. During a configuration download, an
accumulated checksum is calculated after each word (8- or-16 bits) of the bitstream is
downloaded to the FPGA. During the bitstream download, the user may write to a series
of registers in a special window known as the Checksum Page.
After power-on-reset, the checksum and seed are cleared to zero. Just prior to the start
of a configuration download, the seed value is loaded into the checksum. Whenever the
Evaluate Checksum register(s) are written, a new Checksum is calculated. If the new
value does not equal “FF” (or “FFFF” for 16-bit operation), the INIT pin is driven Low to
indicate an error has occurred. Whenever the Seed is written, the Checksum accumula-
tor is also written with the new Seed value.
The bitstream will not be terminated on a Checksum Function error.
Bitstream Errors
The INIT pin is driven Low by the FPGA for a number of reasons. In all cases, the INIT
pin will be driven Low two clocks after the byte which caused the error. Some errors will
cause a bitstream to be terminated. Some will not. If a bitstream is terminated, all config-
uration pins are released by the configuration logic, and the configuration state returns
to Idle.
A bad preamble causes the INIT pin to be driven Low, and causes the bitstream to be
terminated.
A bad window start address or end address causes the INIT pin to be driven Low two
clocks after the third byte of the end address is seen by the device. The bitstream is
terminated.
If the number of windows has been decremented to zero and the expected postamble is
not seen by the device, the INIT pin is driven Low two clocks after the bad byte is seen
by the FPGA. The bitstream is terminated.
During a Check Function, a mismatched write-verify error results in the INIT pin being
driven Low two clocks after the byte. The INIT pin will remain Low until the end of the bit-
stream. The bitstream will NOT terminate.
If the Security Flag bit was set in the previous bitstream, the FPGA will drive the INIT pin
Low two clocks after CON was driven Low by the user. The bitstream will immediately
terminate.
If a checksum error is detected during a bitstream download, the INIT pin is driven Low
two clocks after the write to the Checksum Page. The INIT pin will remain Low until the
end of the bitstream. The bitstream will not terminate.
Table 9.
Checksum Page
byte 0
Evaluate Checksum, bits 7:0
byte 1
Evaluate Checksum, bits 15:8
byte 2
Seed, bits 7:0
byte 3
Seed, bits 15:8
