36
AT40K Series Configuration
1009B–FPGA–03/02
Mode 2: Slave
Parallel
Figure 21.
Stand-alone 2 Microprocessor
A Mode 2 Slave Parallel device is usually configured in a system in one of two ways.
The first is a stand-alone or cascade scheme whereby data comes from a microproces-
sor, see Figure 21.The other is a cascade scheme where the data is driven by a parallel
PROM, and the FPGA is usually downstream from a Mode 6 device, see Figure 22.
Configuration Data Source:
Microprocessor, Parallel
EEPROM, EPROM, PROM
Dedicated Configuration Pins:
RESET, CON, M
0
, M
1
, M
2
, CCLK
Dual-use I/O:
D
0
:D
7
, INIT, LDC, HDC, CS
1,
OTS
Optional Dual-use I/O:
CSOUT, CHECK, D
8
:D
15
IO<0>
IO<1>
IO<2>
IO<3>
IO<4>
IO<5>
IO<6>
IO<7>
IO<8>
IO<9>
IO<10>
IO<11>
IO<12>
IO<13>
IO<14>
IO<15>
IO<16>
IO<17>
IO<18>
IO<20>
IO<21>
IO<22>
IO<23>
IO<24>
IO<19>
IO<25>
IO<26>
IO<27>
IO<28>
IO<29>
IO<30>
IO<31>
Microprocessor
Reset
CLK
WE
M0
M1
M2
OTS
CHECK
CCLK
CS1
DATA <0:7>
RESET
INIT
CON
CSOUT
AT40K
Mode 2
Slave Parallel
Optional IO
Optional IO
VDD
VSS
CLOCK
RESET
