28
AT40K Series Configuration
1009B–FPGA–03/02
Figure 13.
Slave Serial End of Configuration Download
Notes:
1. For a configuration bitstream error, INIT is driven Low on the second rising edge after the bitstream error is detected. In the
above example, the “0” in the second to last bit of the postamble is inserted to produce the error shown. The proper value is
“1”. The error is shown for timing purposes only; under normal circumstances the bitstream download would terminate
prematurely.
2. The pins CSOUT and CHECK are claimed by the configuration interface only if enabled by the control register. Both are
enabled by default after power-on-reset or manual reset.
t
CONH
D0
LAST BIT OF
POSTAMBLE
USER I/O
USER I/O
USER I/O
t
CFG
USER I/O
20K PULL-UP (INTERNAL)
USER I/O
t
DCSOUT
x
x
1
x
x
0
CCLK
CON
LDC
HDC
CSOUT
(2)
INIT
(1)
10K PULL-UP
(INTERNAL)
NO MORE
CLOCKS NEEDED
