10
AT40K Series Configuration
1009B–FPGA–03/02
Holding off
Auto-Configuration
There are two methods by which the user may delay a master Mode 0 auto-configura-
tion. The first is to drive RESET Low during power-on-reset or manual reset and hold the
signal Low until the user is ready to proceed with auto-configuration. The second is to
drive INIT Low with an open drain driver during power-on-reset or manual reset, and
release when the user is ready to proceed with auto-configuration. Both are valid in a
AT40K series device. Assuming the device has completed its configuration clear cycle
and that INIT and RESET are inactive (High), a Mode 0 FPGA starts CCLK and configu-
ration download.
Configuration
Control Register
The AT40K series devices have a 32-bit control register that is written at the beginning
of a configuration download. These bits control various configuration sequence parame-
ters. All bits are set to 0 during a configuration clear cycle. In parallel modes, byte 0 is
loaded first. In serial modes, bit-31 is loaded first. The control register settings are made
in the FPGA Designer IDS Software Options section
•
Go to the
Options
menu on the IDS (Figaro) main window and select
Options
.
•
Choose
AT40K Bitstream
from the topics list
Note:
1. IDS uses names "B0" ~ "B31" for "CR0" ~ "CR31" for the Control Register.
CR
0
:
0 = Reset Address Counter
1 = Retain Address Counter
CR
0
controls the value of the Mode 6 device’s memory address counter after each con-
figuration sequence. The default resets the address up-counter to 000000 after each
configuration download is completed. When this bit is set, the memory address counter
retains its last value. This allows multiple designs to be stored sequentially in an exter-
nal memory device for use in reconfigurable systems.
CR
1
:
Not used (ignored)
CR
2
:
0 = Enable Cascading
1 = Disable Cascading
CR
2
controls the operation of the dual-function I/O CSOUT. When CR
2
is set, the
CSOUT pin is not used by the configuration during downloads.
CR
3
:
0 = Check Function enabled
1 = Check Function disabled
CR
3
controls the operation of the CHECK pin and enables the Check Function. When
CR
3
is set, the CHECK pin is not used by the configuration during downloads.
Table 5.
Control Register
Byte 0
CR
31
CR
30
CR
29
CR
28
CR
27
CR
26
CR
25
CR
24
Byte 1
CR
23
CR
22
CR
21
CR
20
CR
19
CR
18
CR
17
CR
16
Byte 2
CR
15
CR
14
CR
13
CR
12
CR
11
CR
10
CR
9
CR
8
Byte 3
CR
7
CR
6
CR
5
CR
4
CR
3
CR
CR
1
CR
0
