40
AT40K Series Configuration
1009B–FPGA–03/02
Table 15.
Slave Parallel Configuration Timing Parameters @ 5V ± 10% Industrial/Commercial Range
Parameter
Description
Min
Typ
Max
Units
t
PCCLK
Period of CCLK for configuration downloads
30
ns
Period of CCLK for configuration downloads with the check function enabled
1000
ns
t
SCC
Setup time for CON and CS
1
with respect to rising edge of CCLK
6
10
16
ns
t
SCD
Setup time for data with respect to rising edge of CCLK
6
10
16
ns
t
HCD
Hold time for data with respect to rising edge of CCLK
0
0
0
ns
t
SCCCLK
Setup time for CHECK with respect to rising edge of CCLK at the start of a configuration
download.
6
10
16
ns
t
DCI
Delay from rising edge of CCLK to activation of configuration interface at the start of re-
configuration
6
10
16
ns
t
DCSOUT
Delay from rising edge of CCLK to falling edge of CSOUT by upstream device during a
cascade configuration
6
10
16
ns
t
CONH
Delay from rising edge of CCLK to rising edge release of CON at the end of
configuration. Timing is measured with a 50pf load and a 2.7K pull-up resistor on CON.
Actual time will depend on system loading of CON.
130
ns
t
CFG
Delay from rising edge of CCLK to the release of dual-use pins to full user functionality.
6
10
16
ns
