21
AT40K Series Configuration
1009B–FPGA–03/02
Mode 0: Master Serial
Figure 6.
Stand-alone 0 Configurator System Application
In Mode 0, CCLK is driven by the Master Serial AT40K FPGA into an Atmel Configurator
that drives data out its Data pin and into the D0 pin of the FPGA. Each CCLK increments
the Configurator internal address counter, and serial data is presented to the FPGA.
Once the bitstream is completed, CON is released by the FPGA, indicating the device is
completely ready for user operation. Configuration time depends on the frequency of the
internal clock driving CCLK (approximately 1 microsecond), and on the structure of the
bitstream. A full bitstream for the AT40K20 takes about 153 milliseconds to download
(one microsecond per bit of configuration data).
At the end of power-on-reset or manual reset, CON is not pulsed High. For the AT40K
series devices, either the RESET or INIT pin is tied to the Configurator OE/RESET pin,
and CON is tied to the Configurator chip enable (CE). Figure 7 shows the timing of the
configuration interface after power-on-reset or manual reset and at the start of down-
load. Figure 8 shows the timing of the configuration interface after manually initiating a
configuration download from the idle state (without reset). Figure 9 shows the timing of
the configuration interface at the end of configuration download. Table 11 shows the
configuration timing parameters for these timing diagrams.
Configuration Data Source:
Serial EEPROM
Dedicated Configuration Pins:
RESET, CON, M
0
, M
1
, M
2
,
CCLK
Dual-use I/O:
D
0
, INIT, LDC, HDC
Optional Dual-use I/O:
CSOUT, CHECK.OTS
M0
M1
M2
OTS
CHECK
CCLK
D<0>
RESET
INIT
CON
CSOUT
AT40K
Mode 0
Master Serial
CLK
DATA
CE
RESET
CEO
AT17C256
VSS
INIT
OPTIONAL IO
OPTIONAL IO
RESET
