4
AT40K Series Configuration
1009B–FPGA–03/02
M
0
, M
1
, M
2
The mode pins are dedicated TTL threshold inputs that determine the configuration
mode to be used. Table 1 lists the states for each configuration mode. The mode pins
should not be changed during power-on-reset, manual reset, or configuration download.
The user may change the mode pins during configuration idle. These pins have no pull-
up resistors to VDD, so they need to be driven by the user or tied off.
CCLK
CCLK is the configuration clock pin. It is an input or output depending on the mode of
operation. During power-on-reset or manual reset, it is a tri-stated output. During config-
uration download and in Mode 0, it is an output with a typical frequency of 1 MHz. During
configuration download and in all other modes, it is a Schmitt trigger input with approxi-
mately 1V of hysteresis for noise immunity. It is an input during configuration idle, but is
ignored. It is pulled to VDD with a nominal 50K internal resistor.
RESET
RESET is the FPGA configuration manual reset pin. It is available during all configura-
tion states. It initiates a configuration clear cycle and, if operating in Mode 0, an auto-
configuration. It is a dedicated Schmitt trigger input with approximately 1V of hysteresis
for noise immunity. It is pulled to VDD with a nominal 50K internal resistor.
INIT
INIT is a multi-function pin. During power-on-reset and manual reset, the pin functions
as an open drain bi-directional I/O which releases High when the configuration clear
cycle is complete, but can be held Low to hold the configuration in a reset state. Once
released, the FPGA will proceed to either configuration download or idle, as appropriate.
During configuration download, the INIT pin is again an open drain bi-directional pin
which signals if an error is encountered during the download of a configuration bit-
stream. In addition, during the Check Function, the INIT pin drives Low for any
configuration SRAM mismatch (see the description of the Check Function on page 16
for more details). While in open drain mode, the pin is pulled to VDD with a nominal 20K
internal resistor. When not configuring, the INIT pin becomes a fully functional user I/O.
CON
CON is the FPGA configuration start and status pin. It is a dedicated open drain bi-direc-
tional pin. During power-on-reset or manual reset, CON is driven Low by the FPGA. In
Modes 2, 6, or 7, when the FPGA has finished the configuration clear cycle, CON is
released to indicate the device is ready for the user to initiate configuration download.
The user may then drive CON Low to initiate a configuration download. After three clock
cycles, CON is then driven Low by the FPGA until it finishes the download, and it is then
released. In Mode 0, CON is not released by the FPGA at the end of power-on-reset or
manual reset. Instead, CON is controlled by the FPGA until the end of the auto-configu-
ration process. CON is released at the end of configuration download in Mode 0, and the
user may then initiate a manual configuration download by driving CON Low. While in
open drain mode, the pin is pulled to VDD with a nominal 10K internal resistor.
HDC
HDC
is the FPGA “High During Configuration” pin. It is an output, driven High by the
FPGA during power-on-reset, manual reset, and configuration download. During config-
uration idle, the pin is a fully functional user I/O.
Note:
1. All user I/O default to inputs with pull-ups “on”. The HDC pin transitions from driving a
strong “1” to a pull-up “1” after reset. The HDC pin will transition from driving a strong
“1” to the user programmed state at the end of configuration download. If not pro-
grammed, the default state is input with pull-up.
