39
AT40K Series Configuration
1009B–FPGA–03/02
Figure 24.
Slave Parallel End of Configuration Download
Notes:
1. For a configuration bitstream error, INIT is driven Low on the second rising edge after the bitstream error is detected. In the
above example, the “00” in the second to last bit of the postamble is inserted to produce the error shown. The error is shown
for timing purposes only; under normal circumstances the bitstream download would terminate prematurely.
2. The pins CSOUT and CHECK are claimed by the configuration interface only if enabled by the control register. Both are
enabled by default after power-on-reset or manual reset.
3. Data can also be loaded D<0:15> as a 16-bit word.
Figure 25.
Cascade Chain Interface Timing Diagram
Notes:
1. Cascade bitstream is formed by simple concentration of upstream and downstream bitstreams.
2. INIT of upstream and downstream devices are tied together for above example.
3. Data can be driven D<0:15> as a 16-bit word.
NO MORE
CLOCKS NEEDED
t
CONH
D<0:7>
(3)
USER I/O
USER I/O
USER I/O
t
CFG
USER I/O
20K PULL-UP
(INTERNAL)
USER I/O
ACTIVE ONLY IF CASCADE ENABLED
t
DCSOUT
xx
xx
xx
E7
LAST BYTE OF POSTAMBLE
xx
00
CCLK
CON
CS1
INIT
(1)
LDC
HDC
CSOUT
(2)
10K PULL-UP
(INTERNAL)
USER I/O
DOWNSTREAM DEVICE DRIVES ONLY
USER I/O
20K PULL-UP
(INTERNAL)
UPSTREAM DEVICE DRIVES ONLY
BOTH DRIVE
ADDRESS OUT
E7
LAST BYTE OF POSTAMBLE
OF UPSTREAM DEVICE
00
00
B7
00
00
00
00
00
n
n-1
n+1
n+2
n+3
n+4
n+5
n+6
n+7
PREAMBLE OF
DOWNSTREAM DEVICE
FIRST NULL BYTE
OF DOWNSTREAM DEVICE
CCLK
CON
CSOUT (FROM UPSTREAM)
CS1 (TO DOWNSTRAM)
INIT
(2)
LDC
(DOWNSTREAM DEVICE)
D<0:7>
(3)
