23
AT40K Series Configuration
1009B–FPGA–03/02
Figure 8.
Master Serial Start of Re-configuration (without reset)
Notes:
1. INIT is an open drain pin during configuration downloads, so this pin must be driven only by an open drain driver. The pull-up
value should be properly chosen to allow the pin to be pulled High prior to the first rising edge of CCLK. Failure to do so will
not cause the part to abort the download, but may cause the user confusion if the FPGA does drive the pin Low.
2. Parameter t
CE
is taken from the AT17 series datasheet.
3. For configuration interface inputs, t
DCI
indicates the time for the User I/O to tri-state.
4. Users must drive CON Low for 3 rising edge of CCLK, and then should release. During re-configuration, when CON is driven
Low, the EEPROM begins driving immediately, but the FPGA will not claim the configuration interface until after the first ris-
ing edge of CCLK after CON goes Low. The D
0
pin is a dual-use I/O, but must remain an input in order for re-configuration to
operate properly. Failure to do so will cause contention between the Serial EEPROM and the FPGA when CON goes Low.
5. The EEPROM’s OE/RESET pin is wired to the INIT pin of the FPGA in the example wiring shown in Figure 6. The internal
counters of the EEPROM are reset by a Low pulse on the OE/RESET pin. The user must either load both the re-configura-
tion bitstream and the auto-configuration bitstream sequentially into the EEPROM, or pulse the OE/RESET pin Low to reset
the EEPROM and then reload the auto-configuration bitstream.
USER MAY RELEASE
DRIVEN BY USER ONLY
D0
t
CE
(2)
t
DCCLKH
USER I/O
USER I/O
t
DCI
(3)
USER I/O
USER I/O
t
SCCCLK
50K PULL-UP (INTERNAL)
20K PULL-UP (INTERNAL)
USER I/O,
MUST BE AN INPUT
BIT 0
BIT 1
BIT 2
BIT 3
10K PULL-UP
(INTERNAL)
CCLK
CON
(4)
INIT
(1)(5)
CHECK
LDC
HDC
