9
AT40K Series Configuration
1009B–FPGA–03/02
Figure 2.
Configuration Reset State Diagram
The AT40K FPGA allows complete re-configurability down to the byte level. The
CacheLogic
®
architecture lets users reconfigure part of the FPGA while the rest of the
FPGA continues to operate unaffected.
Control of the FPGA system level interface is possible on an AT40K series FPGA. User
I/O, internal Global Set/Reset, and Global and Fast Clocks can be enabled or disabled
during configuration downloads by setting bits in the control register.
User I/O become active as soon as the relevant I/O configuration SRAM is loaded. To
aid system level integration, a bit in the control register (CR
31
) may be set which com-
mands all I/O pins not part of the configuration interface to go tri-stated. This bit is set at
the start of configuration so the very first download can be affected.
Another bit in the control register (CR
30
) may be set to enable (drive Low) the global
reset net during configuration download.
Another set of bits in the control register (CR
27
:CR
16
) may be set to disable (drive High)
each of the global and fast clock input buffers which drive the global clock nets. The
user I/O portion of these buffers is not affected.
Configuration Idle
Configuration
Clear Cycle
RESET
= Low ?
No
RESET
= High?
Yes
No
Release INIT Errn
RESET
= Low ?
No
Yes
INIT
= High?
No
Yes
Sample Mode Pins
RESET
= Low ?
No
Yes
Device
= Master ?
No
Yes
Configuration Download
Yes
(Power-on-Reset)
VDD
> 2.1V
No
Manual Reset
Yes
