344
(4) Mode 3 (8 lane ) - (split vertically into 2)
Using lanes 1 and 2 and lanes 3 and 4, the left half of the image is output in the even and odd numbers; similarly,
using lanes 5 and 6 and lanes 7 and 8, the right half of the image is output in the even and odd numbers.
Given here as an example where the resolution is 4096 × 2048, the dot clock frequency is 594 MHz and the output
bit depth is 10 bits.
・・・
L0~
L2159
D
2040
D
2042
D
2044
D
2046
[9:0]
[9:0]
[9:0]
[9:0]
D
0
[9:0]
D
2
D
4
D
6
・・・
[9:0]
[9:0]
[9:0]
D
2041
[9:0]
D
2043
D
2045
D
2047
[9:0]
[9:0]
[9:0]
[9:0]
・・・
[9:0]
[9:0]
[9:0]
D
1
D
3
D
5
D
7
D
4088
D
4090
D
4092
D
4094
[9:0]
[9:0]
[9:0]
[9:0]
D
2048
[9:0]
D
2050
D
2052
D
2054
・・・
[9:0]
[9:0]
[9:0]
D
4089
[9:0]
D
4091
D
4093
D
4095
[9:0]
[9:0]
[9:0]
[9:0]
・・・
[9:0]
[9:0]
[9:0]
D
2049
D
2051
D
2053
D
2055
L0~
L2159
L0~
L2159
L0~
L2159
L0~
L2159
[9:0]
[9:0]
[9:0]
[9:0]
[9:0]
・・・
[9:0]
[9:0]
[9:0]
[9:0]
[9:0]
[9:0]
[9:0]
[9:0]
・・・
[9:0]
[9:0]
[9:0]
L0~
L2159
[9:0]
[9:0]
[9:0]
[9:0]
[9:0]
・・・
[9:0]
[9:0]
[9:0]
L0~
L2159
[9:0]
[9:0]
[9:0]
[9:0]
[9:0]
・・・
[9:0]
[9:0]
[9:0]
L0~
L2159
D
8
D
10
D
12
D
14
D
2032
D
2034
D
2036
D
2038
D
2033
D
2035
D
2037
D
2039
D
9
D
11
D
13
D
15
D
4080
D
4082
D
4084
D
4086
D
2056
D
2058
D
2060
D
2062
D
4081
D
4083
D
4085
D
4087
D
2057
D
2059
D
2061
D
2063
C
LK
74M
H
z
Lane 1
Lane 2
Lane 3
Lane 4
Lane 5
Lane 6
Lane 7
Lane 8
Summary of Contents for VG-876
Page 1: ...Video Signal Generator VG 876 Instruction Manual Ver 3 40 ...
Page 2: ......
Page 30: ...16 ...
Page 57: ...Chapter 3 TIMING DATA SETTINGS 43 ...
Page 103: ...Chapter 4 PATTERN SETTINGS 89 1 2 3 4 5 6 0 ...
Page 134: ...120 GUI Display Selected port ...
Page 135: ...Chapter 4 PATTERN SETTINGS 121 HEX Display Selected port ...
Page 143: ...Chapter 4 PATTERN SETTINGS 129 ...
Page 177: ...Chapter 6 HDCP SETTINGS AND EXECUTION 163 ...
Page 205: ...Chapter 7 VG 876 SYSTEM SETTINGS 191 ...
Page 223: ...Chapter 8 DATA COPYING ERASING 209 ...
Page 237: ...Chapter 9 USEFUL FUNCTIONS 223 ...
Page 336: ...322 10 5 3 Data transfer method Normal MODE 2Lane output ...
Page 338: ...324 Normal MODE 4Lane output ...
Page 376: ...362 Assignment of each lane ...
Page 378: ...364 Assignment of each lane Lane 1 4 Lane 9 12 Lane 5 8 Lane 13 16 ...
Page 380: ...366 Assignment of each lane Lane1 4 Lane9 12 Lane5 8 Lane 13 16 ...
Page 382: ...368 Assignment of each lane Lane1 8 Lane9 16 ...
Page 384: ...370 Assignment of each lane Lane1 8 Lane9 16 ...
Page 386: ...372 Assignment of each lane Lane1 8 Lane9 16 ...
Page 388: ...374 Assignment of each lane Lane1 4 Lane9 12 Lane5 8 Lane 13 16 ...
Page 390: ...376 Assignment of each lane Lane1 4 Lane9 12 Lane5 8 Lane 13 16 ...
Page 392: ...378 Assignment of each lane Lane1 16 ...
Page 453: ...Chapter 10 INTERFACE SETTINGS 439 Connection figure of VM 1876 MX s ...
Page 464: ...450 Reverse Mode Top Bottom Reverse Mode LR TB ...
Page 466: ...452 Reverse Mode Top Bottom Reverse Mode LR TB ...
Page 468: ...454 Reverse Mode Top Bottom Reverse Mode LR TB ...
Page 495: ...Chapter 10 INTERFACE SETTINGS 481 2 When Video Width is 8 bit ...
Page 496: ...482 3 When Video Width is 10 bit ...
Page 501: ...Chapter 10 INTERFACE SETTINGS 487 2 When iTMDS output ...
Page 504: ......
Page 538: ...524 ...