Chapter 10 INTERFACE SETTINGS
465
10.12.8. HDMI HDCP2.2 Unit
HDMI
CH1
CH2
CH3
CH4
Connector
HDMI x 4
Dot clock
Single Clock mode
<RGB/YCbCr444>
8 bit:
25
– 300 MHz (TMDSCLK 3GHz)
10 bit: 25
– 240 MHz (TMDSCLK 3GHz)
12 bit: 25 - 200 MHz (TMDSCLK 3GHz)
<YCbCr422>
8 bit:
25
– 300 MHz (TMDSCLK 3GHz)
10 bit: 25
– 300 MHz (TMDSCLK 3GHz)
12 bit: 25
– 300 MHz (TMDSCLK 3GHz)
Dual Clock mode
*1
<RGB/YCbCr444>
8 bit:
50 - 600 MHz (TMDSCLK 3GHz)
10 bit: 50
– 480 MHz (TMDSCLK 3GHz)
12 bit: 50 - 400 MHz (TMDSCLK 3GHz)
<YCbCr422>
8 bit:
50 - 600 MHz (TMDSCLK 3GHz)
10 bit: 50 - 600 MHz (TMDSCLK 3GHz)
12 bit: 50 - 600 MHz (TMDSCLK 3GHz)
<YCbCr420>
8 bit:
50 - 600 MHz (TMDSCLK 3GHz)
10 bit: 50 - 480 MHz (TMDSCLK 3GHz)
12 bit: 50 - 400 MHz (TMDSCLK 3GHz)
Quad Clock mode
*2
<RGB/YCbCr444>
8 bit:
100
– 1200 MHz (TMDSCLK 3GHz)
10 bit: 100
– 960 MHz (TMDSCLK 3GHz)
12 bit: 100 - 800 MHz (TMDSCLK 3GHz)
<YCbCr422>
8 bit:
100 - 1200 MHz (TMDSCLK 3GHz)
10 bit: 100 - 1200 MHz (TMDSCLK 3GHz)
12 bit: 100
– 1200 MHz (TMDSCLK 3GHz)
Number of colors
generated
RGB each
8/10/12bit
(
RGB/ YCbCr444/ YCbCr422/ YCbCr420(8bit only) support
)
Audio
Out
HDMI
L-PCM
Sampling: 32kHz, 44.1kHz, 48kHz, 88.2kHz. 96kHz, 176.4kHz, 192kHz
Output frequency : 100Hz to 20kHz
Bit : 16/20/24-bit
Com-
pressed
AAC, AC3
Option
Next generation audio
DSD, Dolby Digital Plus, Dolby True HD,
DTS HD (High Resolution Audio), DTS HD(Master Audio)
COAX
Sampling frequency: 32, 44.1, 48, 88.2, 96, 176.4, 192 kHz
Copy protection
HDCP Ver2.2 or Ver1.4 (depends on Sink device)
Other functions
E-EDID Ver1.4(DDC2B), xvYCC, CEC
*1
Output in parallel using two HDMI ports (CH1-2 / CH3-4). In case of YCbCr420, same signal is output from
each CH.
*2
Output in parallel using four HDMI ports (CH1-2-3-4).
Summary of Contents for VG-876
Page 1: ...Video Signal Generator VG 876 Instruction Manual Ver 3 40 ...
Page 2: ......
Page 30: ...16 ...
Page 57: ...Chapter 3 TIMING DATA SETTINGS 43 ...
Page 103: ...Chapter 4 PATTERN SETTINGS 89 1 2 3 4 5 6 0 ...
Page 134: ...120 GUI Display Selected port ...
Page 135: ...Chapter 4 PATTERN SETTINGS 121 HEX Display Selected port ...
Page 143: ...Chapter 4 PATTERN SETTINGS 129 ...
Page 177: ...Chapter 6 HDCP SETTINGS AND EXECUTION 163 ...
Page 205: ...Chapter 7 VG 876 SYSTEM SETTINGS 191 ...
Page 223: ...Chapter 8 DATA COPYING ERASING 209 ...
Page 237: ...Chapter 9 USEFUL FUNCTIONS 223 ...
Page 336: ...322 10 5 3 Data transfer method Normal MODE 2Lane output ...
Page 338: ...324 Normal MODE 4Lane output ...
Page 376: ...362 Assignment of each lane ...
Page 378: ...364 Assignment of each lane Lane 1 4 Lane 9 12 Lane 5 8 Lane 13 16 ...
Page 380: ...366 Assignment of each lane Lane1 4 Lane9 12 Lane5 8 Lane 13 16 ...
Page 382: ...368 Assignment of each lane Lane1 8 Lane9 16 ...
Page 384: ...370 Assignment of each lane Lane1 8 Lane9 16 ...
Page 386: ...372 Assignment of each lane Lane1 8 Lane9 16 ...
Page 388: ...374 Assignment of each lane Lane1 4 Lane9 12 Lane5 8 Lane 13 16 ...
Page 390: ...376 Assignment of each lane Lane1 4 Lane9 12 Lane5 8 Lane 13 16 ...
Page 392: ...378 Assignment of each lane Lane1 16 ...
Page 453: ...Chapter 10 INTERFACE SETTINGS 439 Connection figure of VM 1876 MX s ...
Page 464: ...450 Reverse Mode Top Bottom Reverse Mode LR TB ...
Page 466: ...452 Reverse Mode Top Bottom Reverse Mode LR TB ...
Page 468: ...454 Reverse Mode Top Bottom Reverse Mode LR TB ...
Page 495: ...Chapter 10 INTERFACE SETTINGS 481 2 When Video Width is 8 bit ...
Page 496: ...482 3 When Video Width is 10 bit ...
Page 501: ...Chapter 10 INTERFACE SETTINGS 487 2 When iTMDS output ...
Page 504: ......
Page 538: ...524 ...