
Chapter 10 INTERFACE SETTINGS
335
(5) Mode 4 (x4 mode) ( 8 lanes ) - Dividing Cross Mode
Using lanes 1 and 3 and lanes 2 and 4, the left half of the image is output in the even and odd numbers; similarly,
using lanes 5 and 7 and lanes 6 and 8, the right half of the image is output in the even and odd numbers.
Given here as an example where the resolution is 1920 × 1080, the dot clock frequency is 594 MHz and the output bit
depth is 10 bits.
・・・
D 952
D 956
[9:0]
[9:0]
[9:0]
[9:0]
D 0
[9:0]
D 4
・・・
[9:0]
[9:0]
[9:0]
[9:0]
[9:0]
[9:0]
[9:0]
[9:0]
・・・
[9:0]
[9:0]
[9:0]
D 1912
D 1916
[9:0]
[9:0]
[9:0]
[9:0]
D 960
[9:0]
D 964
・・・
[9:0]
[9:0]
[9:0]
[9:0]
[9:0]
[9:0]
[9:0]
[9:0]
・・・
[9:0]
[9:0]
[9:0]
[9:0]
[9:0]
[9:0]
[9:0]
[9:0]
・・・
[9:0]
[9:0]
[9:0]
[9:0]
D 955
D 959
[9:0]
[9:0]
[9:0]
[9:0]
・・・
[9:0]
[9:0]
[9:0]
D 3
D 7
[9:0]
[9:0]
[9:0]
[9:0]
[9:0]
・・・
[9:0]
[9:0]
[9:0]
[9:0]
D 1915
D 1919
[9:0]
[9:0]
[9:0]
[9:0]
・・・
[9:0]
[9:0]
[9:0]
D 963
D 967
D 8
D12
D968
D 972
D11
D15
D 971
D 975
D 944
D 948
D 1904
D 1908
D 947
D 951
D 1907
D 1911
L0~
L1079
L0~
L1079
L0~
L1079
L0~
L1079
L0~
L1079
L0~
L1079
L0~
L1079
L0~
L1079
D 953
D 957
D 1
D 5
D9
D13
D 945
D 949
D 954
D 958
D 2
D 6
D10
D14
D 946
D 950
D 1913
D 1917
D 961
D 965
D969
D 973
D 1905
D 1909
D 1914
D 1918
D 962
D 966
D 970
D 974
D 1906
D 1910
C
LK
74M
Hz
Lane 1
Lane 2
Lane 3
Lane 4
Lane 5
Lane 6
Lane 7
Lane 8
Summary of Contents for VG-876
Page 1: ...Video Signal Generator VG 876 Instruction Manual Ver 3 40 ...
Page 2: ......
Page 30: ...16 ...
Page 57: ...Chapter 3 TIMING DATA SETTINGS 43 ...
Page 103: ...Chapter 4 PATTERN SETTINGS 89 1 2 3 4 5 6 0 ...
Page 134: ...120 GUI Display Selected port ...
Page 135: ...Chapter 4 PATTERN SETTINGS 121 HEX Display Selected port ...
Page 143: ...Chapter 4 PATTERN SETTINGS 129 ...
Page 177: ...Chapter 6 HDCP SETTINGS AND EXECUTION 163 ...
Page 205: ...Chapter 7 VG 876 SYSTEM SETTINGS 191 ...
Page 223: ...Chapter 8 DATA COPYING ERASING 209 ...
Page 237: ...Chapter 9 USEFUL FUNCTIONS 223 ...
Page 336: ...322 10 5 3 Data transfer method Normal MODE 2Lane output ...
Page 338: ...324 Normal MODE 4Lane output ...
Page 376: ...362 Assignment of each lane ...
Page 378: ...364 Assignment of each lane Lane 1 4 Lane 9 12 Lane 5 8 Lane 13 16 ...
Page 380: ...366 Assignment of each lane Lane1 4 Lane9 12 Lane5 8 Lane 13 16 ...
Page 382: ...368 Assignment of each lane Lane1 8 Lane9 16 ...
Page 384: ...370 Assignment of each lane Lane1 8 Lane9 16 ...
Page 386: ...372 Assignment of each lane Lane1 8 Lane9 16 ...
Page 388: ...374 Assignment of each lane Lane1 4 Lane9 12 Lane5 8 Lane 13 16 ...
Page 390: ...376 Assignment of each lane Lane1 4 Lane9 12 Lane5 8 Lane 13 16 ...
Page 392: ...378 Assignment of each lane Lane1 16 ...
Page 453: ...Chapter 10 INTERFACE SETTINGS 439 Connection figure of VM 1876 MX s ...
Page 464: ...450 Reverse Mode Top Bottom Reverse Mode LR TB ...
Page 466: ...452 Reverse Mode Top Bottom Reverse Mode LR TB ...
Page 468: ...454 Reverse Mode Top Bottom Reverse Mode LR TB ...
Page 495: ...Chapter 10 INTERFACE SETTINGS 481 2 When Video Width is 8 bit ...
Page 496: ...482 3 When Video Width is 10 bit ...
Page 501: ...Chapter 10 INTERFACE SETTINGS 487 2 When iTMDS output ...
Page 504: ......
Page 538: ...524 ...