406
(1)
MODE0 x4 Mode (Quad Link )
(Non Dividing Mode)
Using Video 1, 2, 3 and 4, the image is output under the pixel assignment given below without splitting the screen.
Given here as an example of the resolution is 1920 × 1080, the dot clock frequency is 594 MHz with the 10 bits
output.
The ×4 mode is an output mode designed for the inspection of FPD which support the Full HD 240 Hz output. By
connecting the output of the VG generator to the IA-1540 (iTMDS-LVDS converter box) and by halving the output in
the converter box,
The explanation concerns the signals of the four channels output from the VG generator. For an explanation
concerning an 8-channel output from LVDS, refer to section
“10.5.3 Data transfer systems (V-By-One HS).”
Video 1
Video 2
Video 3 Video 4
CH1 CH2
Summary of Contents for VG-876
Page 1: ...Video Signal Generator VG 876 Instruction Manual Ver 3 40 ...
Page 2: ......
Page 30: ...16 ...
Page 57: ...Chapter 3 TIMING DATA SETTINGS 43 ...
Page 103: ...Chapter 4 PATTERN SETTINGS 89 1 2 3 4 5 6 0 ...
Page 134: ...120 GUI Display Selected port ...
Page 135: ...Chapter 4 PATTERN SETTINGS 121 HEX Display Selected port ...
Page 143: ...Chapter 4 PATTERN SETTINGS 129 ...
Page 177: ...Chapter 6 HDCP SETTINGS AND EXECUTION 163 ...
Page 205: ...Chapter 7 VG 876 SYSTEM SETTINGS 191 ...
Page 223: ...Chapter 8 DATA COPYING ERASING 209 ...
Page 237: ...Chapter 9 USEFUL FUNCTIONS 223 ...
Page 336: ...322 10 5 3 Data transfer method Normal MODE 2Lane output ...
Page 338: ...324 Normal MODE 4Lane output ...
Page 376: ...362 Assignment of each lane ...
Page 378: ...364 Assignment of each lane Lane 1 4 Lane 9 12 Lane 5 8 Lane 13 16 ...
Page 380: ...366 Assignment of each lane Lane1 4 Lane9 12 Lane5 8 Lane 13 16 ...
Page 382: ...368 Assignment of each lane Lane1 8 Lane9 16 ...
Page 384: ...370 Assignment of each lane Lane1 8 Lane9 16 ...
Page 386: ...372 Assignment of each lane Lane1 8 Lane9 16 ...
Page 388: ...374 Assignment of each lane Lane1 4 Lane9 12 Lane5 8 Lane 13 16 ...
Page 390: ...376 Assignment of each lane Lane1 4 Lane9 12 Lane5 8 Lane 13 16 ...
Page 392: ...378 Assignment of each lane Lane1 16 ...
Page 453: ...Chapter 10 INTERFACE SETTINGS 439 Connection figure of VM 1876 MX s ...
Page 464: ...450 Reverse Mode Top Bottom Reverse Mode LR TB ...
Page 466: ...452 Reverse Mode Top Bottom Reverse Mode LR TB ...
Page 468: ...454 Reverse Mode Top Bottom Reverse Mode LR TB ...
Page 495: ...Chapter 10 INTERFACE SETTINGS 481 2 When Video Width is 8 bit ...
Page 496: ...482 3 When Video Width is 10 bit ...
Page 501: ...Chapter 10 INTERFACE SETTINGS 487 2 When iTMDS output ...
Page 504: ......
Page 538: ...524 ...